1GB, 2GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
Features
DDR3 SDRAM UDIMM
MT8JTF12864A – 1GB
MT8JTF25664A – 2GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as
defined in the component data sheet
• 240-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC3-10600, PC3-8500,
or PC3-6400
• 1GB (128 Meg x 64), 2GB (256 Meg x 64)
• V
DD
= V
DD
Q = +1.5V ±0.075V
• V
DDSPD
= +3.0V to +3.6V
• Reset pin for improved system stability
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Single rank
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Adjustable data-output drive strength
• Serial presence-detect (SPD) EEPROM
• Gold edge contacts
• Lead-free
• Fly-by topology
• Terminated control, command, and address bus
Figure 1:
240-Pin UDIMM (MO-269 R/C A)
PCB height: 30mm (1.18in)
Options
•
Operating temperature
1
Marking
–
Commercial (0°C
≤
T
A
≤
+70°C)
None
–
Industrial (–40°C
≤
T
A
≤
+85°C)
I
• Package
–
240-pin DIMM (lead-free)
Y
• Frequency/CAS latency
–
1.5ns @ CL = 9 (DDR3-1333)
-1G4
2
–
1.5ns @ CL = 10 (DDR3-1333)
-1G3
–
1.87ns @ CL = 7 (DDR3-1066)
-1G1
2
–
1.87ns @ CL = 8 (DDR3-1066)
-1G0
2
–
2.5ns @ CL = 5 (DDR3-800)
-80C
2
–
2.5ns @ CL = 6 (DDR3-800)
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1:
Speed
Grade
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Key Timing Parameters
Data Rate (MT/s)
Industry
Nomenclature
PC3-10600
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
CL = 10 CL = 9
1333
1333
–
–
–
–
1333
–
–
–
–
–
CL = 8
1066
1066
1066
1066
–
–
CL = 7
1066
–
1066
–
–
–
CL = 6
800
800
800
800
800
800
CL = 5
–
–
–
–
800
–
t
RCD
(ns)
13.5
15
RP
(ns)
13.5
15
13.125
15
12.5
15
t
RC
(ns)
49.5
51
50.625
52.5
50
52.5
t
13.125
15
12.5
15
PDF: 09005aef82b21119/Source: 09005aef82b2112c
JTF8c128_256x64AY.fm - Rev. B 6/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Addressing
1GB
8K
16K (A[13:0])
8 (BA[2:0])
1Gb (128 Meg x 8)
1K (A[9:0])
1 (S0#)
2GB
8K
32K (A[14:0])
8 (BA[2:0])
2Gb (256 Meg x 8)
1K (A[9:0])
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Part Number
2
MT8JTF12864A(I)Y-1G4__
MT8JTF12864A(I)Y-1G3__
MT8JTF12864A(I)Y-1G1__
MT8JTF12864A(I)Y-1G0__
MT8JTF12864A(I)Y-80C__
MT8JTF12864A(I)Y-80B__
Module
Density
1GB
1GB
1GB
1GB
1GB
1GB
Configuration
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
Module
Bandwidth
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
Table 4:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M8,
1
2Gb DDR3 SDRAM
Part Number
2
MT8JTF25664A(I)Y-1G4__
MT8JTF25664A(I)Y-1G3__
MT8JTF25664A(I)Y-1G1__
MT8JTF25664A(I)Y-1G0__
MT8JTF25664A(I)Y-80C__
MT8JTF25664A(I)Y-80B__
Notes:
Module
Density
2GB
2GB
2GB
2GB
2GB
2GB
Configuration
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
Module
Bandwidth
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
1. Data sheets for the base device parts can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT8JTF12864AY-1G1D1.
PDF: 09005aef82b21119/Source: 09005aef82b2112c
JTF8c128_256x64AY.fm - Rev. B 6/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved
1GB, 2GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
240-Pin DDR3 UDIMM Front
240-Pin DDR3 UDIMM Back
Symbol
V
SS
DM5
NC
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
NC
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
NC
V
SS
DQ62
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
REF
DQ
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
CKE0
V
DD
BA2
NC
V
DD
A11
A7
V
DD
A5
A4
V
DD
Notes:
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
A2
V
DD
CK1
CK1#
V
DD
V
DD
V
REF
CA
NC
V
DD
A10
BA0
V
DD
WE#
CAS#
V
DD
NC
NC
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SCL
SA2
V
TT
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
V
SS
DQ4
DQ5
V
SS
DM0
NC
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
NC
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
173
174
175
176
177
178
179
180
V
SS
DM3
NC
V
SS
DQ30
DQ31
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
NC
V
SS
NC
RESET#
NC
V
DD
NC
V
DD
A12
A9
V
DD
A8
A6
V
DD
A3
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
203
204
205
206
207
208
209
210
A1
V
DD
V
DD
CK0
CK0#
V
DD
NC
A0
V
DD
BA1
V
DD
RAS#
S0#
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
NC
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
172 NC/A14
1
202
1. Pin 172 is NC for 1GB and A14 for 2GB.
PDF: 09005aef82b21119/Source: 09005aef82b2112c
JTF8c128_256x64AY.fm - Rev. B 6/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved
1GB, 2GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A[14:0]
Pin Descriptions
Type
Description
Input
Address inputs:
Provide the row address for ACTIVATE commands, and the column address and
auto precharge bit for READ/WRITE commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a PRECHARGE command to determine whether the
PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be
precharged, the bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands.. The address inputs also provide the op-code during the mode register
command set
.
A[13:0] (1GB), A[14:0] (2GB).
Input
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register, including MR, EMR,
EMR(2), and EMR(3), is loaded during the LOAD MODE command.
Input
Clock:
CK0 and CK0# are differential clock inputs. All contorl, command, and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data
(DQ and DQS/DQS#) is referenced to the crossings of CK and CK#. CK1, CK1# are terminated.
Input
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking
circuitry on the DDR3 SDRAM.
Input
Input data mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is designed to match that of the DQ and DQS
pins.
Input
On-die termination:
ODT (registered HIGH) enables termination resistance internal to the DDR3
SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS,DQS#, and DM. The ODT
input will be ignored if disabled via the LOAD MODE command.
Input
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being entered.
Input
Reset:
RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input receiver is a CMOS
input and is defined as a rail-to-rail signal with DC HIGH
≥
0.8 x V
DD
and DC LOW
≤
0.2 x V
DD
. RESET#
assertion and desertion are asynchronous.
Input
Presence-detect address inputs:
These pins are used to configure the SPD EEPROM address range.
Input
Serial clock for presence-detect:
SCL is used to synchronize presence-detect data transfer to
and from the module.
Input
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command decoder.
With both inputs HIGH, all outputs of the register(s) are disabled except for CKE and ODT. CKE, ODT
and chip select remain in previous state when both outputs are high.
I/O
I/O
Data input/output:
Bidirectional data bus.
Data strobe:
Output with read data. Input with write data for source-synchronous operation. Edge-
aligned with read data. Center-aligned with write data. DQS# is only used when the differential
data strobe mode is enabled via the LOAD MODE command.
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses and data into
and out of the SPD EEPROM on the module.
BA[2:0]
CK[1:0],
CK0#[1:0]
CKE0
DM[7:0]
ODT0
RAS#, CAS#,
WE#
RESET#
SA[2:0]
SCL
S0#
DQ[63:0]
DQS[7:0],
DQS#[7:0]
SDA
V
DD
V
DDSPD
V
REF
DQ
V
REF
CA
V
SS
V
TT
NC
I/O
Supply
Power supply:
1.5V ±0.075V.
Supply
Serial EEPROM positive power supply:
+3.0V to +3.6V.
Supply
Reference voltage:
DQ, DM (V
DD
/2).
Supply
Reference voltage:
Control, command, and address (V
DD
/2).
Supply Ground.
Supply
Termination voltage:
Used for control, command, and address (V
DD
/2).
–
No connect:
These pins are not connected on the module.
PDF: 09005aef82b21119/Source: 09005aef82b2112c
JTF8c128_256x64AY.fm - Rev. B 6/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved
1GB, 2GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
S0#
DQS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4#
DQS4
DM4
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U5
DQ
DQ
DQ
DQ
ZQ
U1
DQS1#
DQS1
DM1
V
SS
DQS5#
DQS5
DM5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
V
SS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U2
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS2#
DQS2
DM2
V
SS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3#
DQS3
DM3
V
SS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQS6#
DQS6
DM6
V
SS
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U6
DQ
DQ
DQ
DQ
ZQ
U3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
V
SS
BA[2:0]
A[14/13:0]
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQS7#
DQS7
DM7
V
SS
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U7
DQ
DQ
DQ
DQ
ZQ
U4
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
V
SS
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U8
DQ
DQ
DQ
DQ
ZQ
BA[2:0]: DDR3 SDRAM
A[14/13:0]: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
WE#: DDR3 SDRAM
CKE0: DDR3 SDRAM
ODT0: DDR3 SDRAM
RESET#: DDR3 SDRAM
SCL
U9
SPD EEPROM
WP A0
A1
A2
SDA
CK0
CK0#
CK1
CK1#
DDR3 SDRAM x8
V
SS
SA0 SA1 SA2
V
DDSPD
V
DD
V
TT
V
REF
CA
V
TT
V
REF
DQ
V
SS
V
DD
SPD EEPROM
DDR3 SDRAM
Control, command, and address termination
DDR3 SDRAM
DDR3 SDRAM
DDR3 SDRAM
Clock, command, control, and address line terminations:
CKE0, A[14/13:0],
RAS#, CAS#, WE#,
S0#, ODT0, BA[2:0]
DDR3
SDRAM
DDR3
SDRAM
CK0
CK0#
Notes:
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is
tied to ground. It is used for the calibration of the component’s ODT and output driver.
PDF: 09005aef82b21119/Source: 09005aef82b2112c
JTF8c128_256x64AY.fm - Rev. B 6/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved
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