2GB (x64, DR) 204-Pin DDR3 SDRAM SODIMM
Features
DDR3 SDRAM SODIMM
MT16JSF25664H – 2GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as
defined in the component data sheet
• 204-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC3-10600, PC3-8500,
or PC3-6400
• 2GB (256 Meg x 64)
• V
DD
= 1.5V ±0.075V
• V
DDSPD
= +3.0V to +3.6V
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Dual rank
• On-board I
2
C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Pb-free
• Fly-by topology
• Terminated control, command, and address bus
Figure 1:
204-Pin SODIMM (MO-268 R/C F)
PCB height: 30.0mm (1.181in)
Options
Marking
• Operating temperature
1
–
Commercial (0°C
≤
T
A
≤
+70°C)
None
–
Industrial (–40°C
≤
T
A
≤
+85°C)
I
• Package
–
204-pin DIMM
Y
• Frequency/CAS latency
–
1.5ns @ CL = 8 (DDR3-1333)
-1G5
–
1.5ns @ CL = 9 (DDR3-1333)
-1G4
2
–
1.5ns @ CL = 10 (DDR3-1333)
-1G3
–
1.87ns @ CL = 7 (DDR3-1066)
-1G1
–
1.87ns @ CL = 8 (DDR3-1066)
-1G0
2
–
2.5ns @ CL = 5 (DDR3-800)
-80C
2
–
2.5ns @ CL = 6 (DDR3-800)
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1:
Speed
Grade
-1G5
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Key Timing Parameters
Data Rate (MT/s)
Industry
Nomenclature
PC3-10600
PC3-10600
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
CL = 10
1333
1333
1333
–
–
–
–
CL = 9
1333
1333
–
–
–
–
–
CL = 8
1333
1066
1066
1066
1066
–
–
CL = 7
1066
1066
–
1066
–
–
–
CL = 6
800
800
800
800
800
800
800
CL = 5
800
–
–
–
–
800
–
t
RCD
(ns)
12
13.5
15
RP
(ns)
12
13.5
15
13.125
15
12.5
15
t
RC
(ns)
48
49.5
51
50.625
52.5
50
52.5
t
13.125
15
12.5
15
PDF: 09005aef83021ee3/Source: 09005aef83021f5a
JSF16C256x64H.fm - Rev. A 3/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2GB (x64, DR) 204-Pin DDR3 SDRAM SODIMM
Features
Table 2:
Parameter
Addressing
2GB
8K
16K (A[13:0])
8 (BA[2:0])
1Gb (128 Meg x 8)
1K (A[9:0])
2 (S0#, S1#)
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Table 3:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Part Number
2
MT16JSF25664H(I)Y-1G5__
MT16JSF25664H(I)Y-1G4__
MT16JSF25664H(I)Y-1G3__
MT16JSF25664H(I)Y-1G1__
MT16JSF25664H(I)Y-1G0__
MT16JSF25664H(I)Y-80C__
MT16JSF25664H(I)Y-80B__
Notes:
Module
Density
2GB
2GB
2GB
2GB
2GB
2GB
2GB
Configuration
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
Module
Bandwidth
10.6 GB/s
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
8-8-8
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT16JSF25664HY-1G1D1.
PDF: 09005aef83021ee3/Source: 09005aef83021f5a
JSF16C256x64H.fm - Rev. A 3/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved
2GB (x64, DR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4:
Pin Assignments
204-Pin DDR3 SODIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
V
REF
DQ
V
SS
DQ0
DQ1
V
SS
DM0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
A9
V
DD
A8
A5
V
DD
A3
A1
V
DD
CK0
CK0#
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
V
DD
A10
BA0
V
DD
WE#
CAS#
V
DD
A13
S1#
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
201
203
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SA0
SA1
V
TT
204-Pin DDR3 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
V
SS
DQ4
DQ5
V
SS
DQS0#
DQS0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
RESET#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2
V
SS
DQ22
DQ23
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
V
SS
DQ28
DQ29
V
SS
DQ3#
DQ3
V
SS
DQ30
DQ31
V
SS
CKE1
V
DD
NC
NC
V
DD
A11
A7
V
DD
A6
A4
V
DD
A2
A0
V
DD
CK1
CK1#
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
V
DD
BA1
RAS#
V
DD
S0#
ODT0
V
DD
ODT1
NC
V
DD
V
REF
CA
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
V
SS
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
200
202
204
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
SDA
SCL
V
TT
198 EVENT#
199 V
DDSPD
PDF: 09005aef83021ee3/Source: 09005aef83021f5a
JSF16C256x64H.fm - Rev. A 3/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved
2GB (x64, DR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Table 5:
Symbol
A[13:0]
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly”
during CAS commands. The address inputs also provide the op-code during the mode
register command set
.
A[13:0] address the 1Gb DDR3 devices.
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register
(MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of the DQS. Although the DM pins are input-only, the DM loading is designed
to match that of the DQ and DQS pins.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be
ignored if disabled via the LOAD MODE command.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
RESET# is an active LOW CMOS input referenced to V
SS
.The RESET# input receiver is
a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 × V
DD
Q and DC LOW
≤
0.2
× V
DD
Q. RESET# assertion and deassertion are asynchronous. System applications will most
likely be unterminated, heavily loaded, and have very slow slew rates. A slow slew rate
receiver design is recommended along with implementing on-chip noise filtering to
prevent false triggering (RESET# assertion minimum pulse width is 100ns).
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
These pins are used to configure the temperature sensor/SPD
EEPROM address range on the I
2
C bus.
Serial clock for temperature sensor/SPD EEPROM:
SCL is used to synchronize the
communication to and from the temperature sensor/SPD EEPROM.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the temperature sensor/SPD EEPROM on the module on the I
2
C bus.
BA[2:0]
Input
CK0, CK0#,
CK1, CK1#
CKE0, CKE1
DM[7:0]
Input
Input
Input
ODT0, ODT1
Input
RAS#, CAS#,
WE#
RESET#
Input
Input
(LVCMOS)
S0#, S1#
SA[2:0]
SCL
DQ[63:0]
DQS[7:0],
DQS#[7:0]
SDA
EVENT#
V
DD
V
DDSPD
V
REF
CA
Input
Input
Input
I/O
I/O
I/O
Output
Temperature event:
The EVENT# pin is asserted by the temperature sensor when critical
(open drain) temperature thresholds have been exceeded.
Supply
Supply
Supply
Power supply:
1.5V ±0.075V. The component V
DD
and V
DD
Q are connected to the
module V
DD
.
Temperature sensor/SPD EEPROM power supply:
+3.0V to +3.6V.
Reference voltage:
Control, command, and address (V
DD
/2).
PDF: 09005aef83021ee3/Source: 09005aef83021f5a
JSF16C256x64H.fm - Rev. A 3/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved
2GB (x64, DR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Table 5:
Symbol
V
REF
DQ
V
SS
V
TT
NC
Pin Descriptions (continued)
Type
Supply
Supply
Supply
–
Description
Reference voltage:
DQ, DM (V
DD
/2).
Ground.
Termination voltage:
Used for control, command, and address (V
DD
/2).
No connect:
These pins are not connected on the module.
PDF: 09005aef83021ee3/Source: 09005aef83021f5a
JSF16C256x64H.fm - Rev. A 3/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved
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