CBTW28DD14
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4
applications
Rev. 7.1 — 3 August 2015
Product data sheet
1. General description
This 14-bit bus switch/multiplexer (MUX) is designed for 1.5 V or 1.8 V supply voltage
operation, POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling and CMOS
select input levels. It is designed for operation in DDR2, DDR3 or DDR4 memory bus
systems.
The CBTW28DD14 has a 1 : 2 switch or 2 : 1 multiplex topology and offers a 14-bit wide
bus. Each 14-bit wide A-port can be switched to one of two ports B and C, for all bits
simultaneously. The selection of the port is by a simple CMOS input (SELect). Another
CMOS input (ENable) is available to allow all ports to be disconnected. Each port is
non-directional due to the use of FET switches, allowing a multitude of applications
requiring high-bandwidth switching or multiplexing.
The SEL and EN input signals are designed to operate transparently as CMOS input level
signals in both 1.5 V and 1.8 V supply voltage conditions.
CBTW28DD14 uses NXP proprietary high-speed switch architecture providing high
bandwidth, very little insertion loss at low frequency, and very low propagation delay,
allowing use in many applications requiring switching or multiplexing of high-speed
signals. It is available in a 4.5 mm
4.5 mm TFBGA48 package with 0.5 mm ball pitch, for
optimal size versus board layout density considerations. It is characterized for operation
from
10 C
to +85
C.
2. Features and benefits
2.1 Topology
14-bit bus width
1 : 2 switch/MUX topology
Bidirectional operation
Simple CMOS select pin (SEL)
Simple CMOS enable pin (EN)
2.2 Performance
2.5 GHz bandwidth
Low ON insertion loss
Low crosstalk
High OFF isolation
POD_12, SSTL_12, SSTL_135, SSTL_15 or SSTL_18 signaling
NXP Semiconductors
CBTW28DD14
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
Low R
ON
(10
typical)
2.3 General attributes
1.5 V or 1.8 V supply voltage operation
Very low supply current (300
A
typical)
ESD robustness exceeds 3 kV HBM, 1 kV CDM
Available in TFBGA48 package, 4.5 mm
4.5 mm
0.8 mm size, 0.5 mm pitch,
Pb-free/Dark Green
3. Applications
DDR2/DDR3/DDR4 memory bus systems
Systems requiring high-speed multiplexing
4. Ordering information
Table 1.
Ordering information
Topside
marking
W2814
2814A
Package
Name
TFBGA48
TFBGA48
Description
plastic thin fine-pitch ball grid array package; 48 balls;
body 4.5
4.5
0.8 mm
plastic thin fine-pitch ball grid array package; 48 balls;
body 4.5
4.5
0.8 mm, Cu-OSP leadframe
Version
SOT1155-1
SOT1155-1
Type number
CBTW28DD14ET
CBTW28DD14AET
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
Package
Packing method
Minimum
order
quantity
4000
4000
Temperature
Type number
CBTW28DD14ET
CBTW28DD14AET
CBTW28DD14ET,118 TFBGA48
CBTW28DD14AETJ
TFBGA48
Reel 13” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
T
amb
=
10 C
to +85
C
T
amb
=
10 C
to +85
C
CBTW28DD14
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7.1 — 3 August 2015
2 of 14
NXP Semiconductors
CBTW28DD14
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
5. Functional diagram
V
DD
SEL
EN
B[0:13]
host side B
CBTW28DD14
14-bit
2 : 1 MUX/switch
A[0:13]
DRAM side
C[0:13]
host side C
GND
002aae969
Fig 1.
Functional diagram
6. Pinning information
6.1 Pinning
ball A1
index area
1
A
B
C
D
E
F
G
H
002aae970
CBTW28DD14ET
2
3
4
5
6
7
8
1
A
B
C
D
E
F
G
H
Transparent top view
B9
B10
B11
C11
B12
B13
A13
A12
2
B8
C9
C10
EN
C12
C13
A11
A10
A9
A8
GND V
DD
A7
A6
A4
A5
3
B7
C8
4
C7
5
C6
6
B6
C5
7
B5
C4
C3
SEL
C1
C0
A2
A3
8
B4
B3
B2
C2
B1
B0
A0
A1
GND V
DD
002aae971
Transparent top view
Fig 2.
Pin configuration for TFBGA48
Fig 3.
Ball mapping
CBTW28DD14
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7.1 — 3 August 2015
3 of 14
NXP Semiconductors
CBTW28DD14
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
6.2 Pin description
Table 3.
Symbol
A[0:13]
B[0:13]
C[0:13]
SEL
Pin description
Pin
Type
Description
14-bit wide input/output, port A
14-bit wide input/output, port B
14-bit wide input/output, port C
CMOS input signal.
When SEL = LOW, port A and
port B are mutually connected.
When SEL = HIGH, port A and
port C are mutually connected.
EN
D2
CMOS input
CMOS input signal.
When LOW, all ports are mutually
isolated.
When HIGH, connection is set using
the SEL input signal.
V
DD
GND
B5, G5
B4, G4
supply
ground
supply voltage connection
ground connection
G8, H8, G7, H7, G6, H6, H5, high-speed I/O
H4, H3, G3, H2, G2, H1, G1
F8, E8, C8, B8, A8, A7, A6,
A3, A2, A1, B1, C1, E1, F1
F7, E7, D8, C7, B7, B6, A5,
A4, B3, B2, C2, D1, E2, F2
D7
high-speed I/O
high-speed I/O
CMOS input
CBTW28DD14
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7.1 — 3 August 2015
4 of 14
NXP Semiconductors
CBTW28DD14
14-bit bus switch/multiplexer for DDR2/DDR3/DDR4 applications
7. Functional description
Refer to
Figure 1 “Functional diagram”.
The CBTW28DD14 uses a 1.5 V or 1.8 V power supply. All signal paths are implemented
using high-bandwidth pass-gate technology and are non-directional. No clock or reset
signal is needed for the multiplexer to function. The switch position for the channels is
selected using the select signal SEL. The detailed operation is described in
Section 7.1.
7.1 Function selection
The internal multiplexer switch position is controlled by two logic inputs, SEL and EN, as
described in
Table 4.
When a channel is not being used, Port B and Port C of this channel should be tied to
ground. For example, if Channel 2 is not used, B2 and C2 should be tied to ground and A2
should be left open.
Table 4.
Function selection
X = don’t care.
Inputs
EN
LOW
HIGH
HIGH
SEL
X
LOW
HIGH
A
B
OFF (isolating)
ON (conducting)
OFF (isolating)
Switch position
A
C
OFF (isolating)
OFF (isolating)
ON (conducting)
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
T
case
V
ESD
Parameter
supply voltage
case temperature
electrostatic discharge
voltage
for operation within
specification
HBM
CDM
[1]
[2]
Conditions
Min
0.3
40
-
-
Max
+2.5
+85
3000
1000
Unit
V
C
V
V
[1]
[2]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing. Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing,
Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
CBTW28DD14
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7.1 — 3 August 2015
5 of 14
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