®
RT7302
Primary-Side-Regulation Dimmable LED Driver Controller
with Active PFC
General Description
The RT7302 is a constant current LED driver with active
power factor correction. It supports high power factor
across a wide range of line voltages, and it drives the
converter in the Quasi-Resonant (QR) mode to achieve
higher efficiency. By using Primary Side Regulation (PSR),
the RT7302 controls the output current accurately without
a shunt regulator and an opto-coupler at the secondary
side, reducing the external component count, the cost,
and the volume of the driver board.
The RT7302 is designed to be compatible with PWM
Dimming. The output current can be modulated by the
duty ratio of the external PWM dimming signal.
An in-house design High Voltage (HV) start-up device is
integrated in the RT7302 to minimize the power loss and
shorten the start-up time.
The RT7302 embeds comprehensive protection functions
for robust designs, including LED open-circuit protection,
LED short-circuit protection, output diode short-circuit
protection, VDD Under-Voltage Lockout (UVLO), VDD
Over-Voltage Protection (VDD OVP), Over-Temperature
Protection (OTP), and cycle-by-cycle current limitation.
Features
Tight LED Current Regulation
No Opto-Coupler and TL431 Required
Power Factor Correction (PFC)
Compatible with PWM Dimming
Built-in HV Start-up Device
Quasi-Resonant
Maximum/Minimum Switching
Frequency
Clamping
Input Voltage Feed-Forward Compensation
Maximum/Minimum On-Time Limitation
Wide VDD Voltage Range (up to 25V)
Multiple Protection Features
½
LED Open-Circuit Protection
LED Short-Circuit Protection
½
Output Diode Short-Circuit Protection
½
VDD Under-Voltage Lockout
½
VDD Over-Voltage Protection
½
Over-Temperature Protection
½
Cycle-by-Cycle Current Limit
RoHS Compliant and Halogen Free
½
Applications
AC/DC LED Lighting driver
Simplified Application Circuit
Flyback Converter
Line
BD
TX1
D
OUT
C
OUT
RT7302
HV
MULT
R
M2
COMP
C
COMP
GND
ZCD
D
AUX
VDD
C
VDD
R
ZCD1
GD
CS
R
PC
R
CS
C
COMP
Buck-Boost Converter
V
OUT+
Line
BD
TX1
D
OUT
C
OUT
V
OUT+
GD
CS
COMP
GND
ZCD
D
AUX
VDD
C
VDD
R
ZCD1
R
PC
R
CS
Q1
V
OUT-
C
SIN
Neutral
R
M2
R
M1
R
HV
C
SIN
Neutral
R
M1
R
HV
V
OUT-
Q1
RT7302
HV
MULT
R
ZCD2
R
ZCD2
Copyright
©
2015 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS7302-03 May 2015
www.richtek.com
1
RT7302
Ordering Information
RT7302
Package Type
S : SOP-8
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
½
Marking Information
RT7302GS : Product Number
RT7302
GSYMDNN
YMDNN : Date Code
Pin Configurations
(TOP VIEW)
HV
GND
COMP
MULT
2
3
4
8
7
6
5
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
VDD
GD
CS
ZCD
½
SOP-8
Functional Pin Description
Pin No.
1
2
3
4
5
6
7
8
Pin Name
HV
GND
COMP
MULT
ZCD
CS
GD
VDD
High Voltage Input for Startup.
Ground of the Controller.
Compensation Node. Output of the internal trans-conductance amplifier.
Input for Line Voltage Signal. This pin is used to sense the line voltage by resistor divider
to achieve dimming function.
Zero Current Detection Input. This pin is used to sense the voltage at auxiliary winding of
the transformer.
Current Sense Input. Connect this pin to the current sense resistor.
Gate Driver Output for External Power MOSFET.
Supply Voltage (V
DD
) Input. The controller will be enabled when V
DD
exceeds V
TH_ON
and disabled when V
DD
is lower than V
TH_OFF
.
Pin Function
Copyright
©
2015 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
DS7302-03 May 2015
RT7302
Function Block Diagram
HV
ZCD
Clamping
Circuit
V
MULT
Feed-Forward
Compensation
Valley
Detector
HV Start-Up
Control
Ramp
Generator
Starter
Circuit
+
Under
Voltage
Lockout
(16V/9V)
VDD Over
Voltage
Protection
V
CLAMP
13V
VDD
Constant Current Control
I
CS
Output Over
Voltage
Protection
L : Open
H : Closed
-
Constant On-Time
Comparator
PWM
Control
Logic
VDD OVP
V
CS_CL
-
1V
Current Limit
Comparator
Output Diode
Short Circuit
Protection
Over
Temperature
Protection
OTP
+
PWM
Gate
Driver
R
GD
GD
GND
CS
Leading
Edge
Blanking
V
MULT
Dimming
Comparator
+
-
V
MULT_EN
/ V
MULT_DS
150mV / 100mV
Output OVP
MULT
COMP
Copyright
©
2015 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS7302-03 May 2015
www.richtek.com
3
RT7302
Operation
Critical-Conduction Mode (CRM) with Constant
On-Time Control
Figure 1 shows a typical flyback
converter with input voltage
(V
IN
). When main switch Q1 is turned on with a fixed on-
time (t
ON
), the peak current (I
L_PK
) of the magnetic inductor
(L
m
) can be calculated by the following equation :
V
I
L_PK
=
IN
t
ON
L
m
TX1
I
L
V
IN
+
Primary-Side Constant-Current Regulation
The RT7302 needs no shunt regulator and opto-coupler
at the secondary side to achieve the output current
regulation. Figure 3 shows several key waveforms of a
conventional flyback converter in Quasi-Resonant (QR)
mode, in which V
AUX
is the voltage on the auxiliary winding
of the transformer.
V
DS
V
IN
0
GD
(V
GS
)
V
AUX
0
D
OUT
+
C
OUT
V
OUT
-
I
OUT
R
OUT
L
m
Q1
(V
OUT
+ V
f
) x N
A
/ N
S
Figure 1. Typical Flyback Converter
If the input voltage is the output voltage of the full-bridge
rectifier with sinusoidal input voltage (V
IN_PK
x sin(θ)), the
inductor peak current (I
L_PK
) can be expressed as the
following equation :
I
Q1
V
IN
x N
A
/ N
P
Clamped by
controller
I
DOUT
I
L_PK
=
V
IN_PK
sin(θ)
t
ON
L
m
Figure 3. Key Waveforms of a Flyback Converter
When the converter operates in CRM with constant on-
time control, the envelope of the peak inductor current
will follow the input voltage waveform with in-phase. Thus,
high power factor can be achieved, as shown in Figure 2.
Voltage Clamping Circuit
The RT7302 provides a voltage clamping circuit at ZCD
pin since the voltage on the auxiliary winding is negative
when the main switch is turned on. The lowest voltage on
ZCD pin is clamped near zero to prevent the IC from being
damaged by the negative voltage. Meanwhile, the sourcing
ZCD current (I
ZCD_SH
), flowing through the upper resistor
(R
ZCD1
), is sampled and held to be a line-voltage-related
signal for propagation delay compensation. The RT7302
embeds the programmable propagation delay
compensation through CS pin. A sourcing current I
CS
(equal to I
ZCD_SH
x K
PC
) applies a voltage offset (I
CS
x
R
PC
) which is proportional to line voltage on CS to
compensate the propagation delay effect. Thus, the output
current can be equal at high and low line voltage.
V
IN
I
L_PK
Input Voltage
Peak Inductor Current
I
in_avg
I
DOUT
Average Input Current
Output Diode Current
I
Q1_DS
MOSFET Current
V
Q1_GS
MOSFET Gate Voltage
Figure 2. Inductor Current of CRM with Constant
On-Time Control
Copyright
©
2015 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS7302-03 May 2015
RT7302
Quasi-Resonant Operation
For improving converter's efficiency, the RT7302 detects
valleys of the Drain-to-Source voltage (V
DS
) of main switch
and turns on it near the selected valley. For the valley
detections, a pulse of the
“valley
signal” is generated
after a 500ns (typ.) delay time which starts at which the
voltage (V
ZCD
) on ZCD pin goes down and reaches the
voltage threshold (V
ZCDT
, 0.4V typ.). During the rising of
the V
ZCD
, the V
ZCD
must reach the voltage threshold
(V
ZCDA
, 0.5V typ.). Otherwise, no pulse of the
“valley
signal” is generated. Moreover, if the timing when the
falling V
ZCD
reaches V
ZCDT
is not later than a mask time
(t
MASK
, 2μs typ.) then the valley signal will be masked and
regards as no valley, as shown in Figure 4.
PWM
½
½
PWM
t
START
Valley
Signal
PWM
t
S(MIN)
Valley
Signal
PWM
t
S(MIN)
Valley
Signal
PWM
t
S(MIN)
5µs
……
……
½
½
V
ZCD
V
ZCDA
V
ZCDT
½
½
Valley
Signal
500ns
t
MASK
Figure 5. PWM Triggered Method
HV Start-up Device
Figure 4. Valley Signal Generating Method
Figure 5 illustrates how valley signal triggers PWM. If no
valley signal
is detected for a long time, the next PWM is
triggered by a starter circuit at the end of the interval (t
START
,
130μs typ.) which starts at the rising edge of the previous
PWM signal. A blanking time (t
S(MIN)
, 8.5μs typ.), which
starts at the rising edge
of the previous PWM signal, limits
minimum switching period. When the t
S(MIN)
interval is
on-going, all of valley signals are not allowed to trigger
the next PWM signal. After the end of the t
S(MIN)
interval,
the coming valley will trigger the next PWM signal. If one
or more valley signals are detected during the t
S(MIN)
interval and no valley is detected after the end of the t
S(MIN)
interval, the next PWM signal will be triggered
automatically at the end of the t
S(MIN)
+ 5μs (typ.).
An in-house design 500V start-up device is integrated in
the RT7302 to minimize the power loss and shorten the
start-up time. The HV start-up device will be turned on
during start-up period and be turned off during normal
operation. It guarantees fast start-up time and no power
loss in this path during normal operation. A 10kΩ resistor
is recommended to be connected in series with HV pin.
Feed-Forward Compensation
The MULT pin is a high impedance input pin used to detect
the line input voltage. A proper voltage divider and a
capacitor should be applied to sense the rectified input
voltage at the output of bridge diode rectifier. Since the
MULT voltage is proportional to the rectified input voltage,
it is used to generate a feed-forward signal, the peak of
the MULT voltage, to compensate the slope of the ramp,
Copyright
©
2015 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
DS7302-03 May 2015
www.richtek.com
5
½
½
Valley
Signal
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