Hitachi Single-Chip Microcomputer
H8/3035 Series
H8/3035, H8/3034, H8/3033
Hardware Manual
Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the
whole or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from
accidents or any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the
characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no
responsibility for any intellectual property claims or other problems that may result from
applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any
third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support systems. Buyers of
Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to
use the products in MEDICAL APPLICATIONS.
Contents
Contents ..... .....................................................................................................i
Preface ....... .....................................................................................................1
Section 1 Overview ........................................................................................3
1.1 Overview ........................................................................................................................ 3
1.2 Block Diagram................................................................................................................ 7
1.3 Pin Description ............................................................................................................... 8
1.3.1 Pin Arrangement................................................................................................ 8
1.3.2 Pin Functions ..................................................................................................... 9
1.4 Pin Functions .................................................................................................................. 12
Section 2 CPU................................................................................................17
2.1 Overview ........................................................................................................................ 17
2.1.1 Features ............................................................................................................. 17
2.1.2 Differences from H8/300 CPU ........................................................................... 18
2.2 CPU Operating Modes .................................................................................................... 18
2.3 Address Space................................................................................................................. 19
2.4 Register Configuration .................................................................................................... 20
2.4.1 Overview ........................................................................................................... 20
2.4.2 General Registers............................................................................................... 21
2.4.3 Control Registers ............................................................................................... 22
2.4.4 Initial CPU Register Values ............................................................................... 23
2.5 Data Formats................................................................................................................... 23
2.5.1 General Register Data Formats .......................................................................... 24
2.5.2 Memory Data Formats ....................................................................................... 26
2.6 Instruction Set................................................................................................................. 27
2.6.1 Instruction Set Overview.................................................................................... 27
2.6.2 Instructions and Addressing Modes.................................................................... 28
2.6.3 Tables of Instructions Classified by Function..................................................... 29
2.6.4 Basic Instruction Formats .................................................................................. 38
2.6.5 Notes on Use of Bit Manipulation Instructions................................................... 39
2.7 Addressing Modes and Effective Address Calculation..................................................... 39
2.7.1 Addressing Modes ............................................................................................. 39
2.7.2 Effective Address Calculation............................................................................ 42
2.8 Processing States............................................................................................................. 46
2.8.1 Overview ........................................................................................................... 46
2.8.2 Program Execution State.................................................................................... 47
2.8.3 Exception-Handling State .................................................................................. 47
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2.8.4 Exception-Handling Sequences.......................................................................... 48
2.8.5 Reset State......................................................................................................... 49
2.8.6 Power-Down State ............................................................................................. 49
2.9 Basic Operational Timing ............................................................................................... 50
2.9.1 Overview ........................................................................................................... 50
2.9.2 On-Chip Memory Access Timing ...................................................................... 50
2.9.3 On-Chip Supporting Module Access Timing...................................................... 51
2.9.4 Access to External Address Space...................................................................... 52
Section 3 MCU Operating Modes .................................................................. 53
3.1 Overview ........................................................................................................................ 53
3.1.1 Operating Mode Selection ................................................................................. 53
3.1.2 Register Configuration....................................................................................... 53
3.2 Mode Control Register (MDCR) ..................................................................................... 54
3.3 System Control Register (SYSCR).................................................................................. 55
3.4 Operating Mode Descriptions.......................................................................................... 57
3.4.1 Mode 1 .............................................................................................................. 57
3.4.2 Mode 2 .............................................................................................................. 57
3.4.3 Mode 3 .............................................................................................................. 57
3.5 Pin Functions in Each Operating Mode ........................................................................... 57
3.6 Memory Map in Each Operating Mode ........................................................................... 58
Section 4 Exception Handling ........................................................................ 61
4.1 Overview ........................................................................................................................ 61
4.1.1 Exception Handling Types and Priority.............................................................. 61
4.1.2 Exception Handling Operation........................................................................... 61
4.1.3 Exception Vector Table ..................................................................................... 62
4.2 Reset............................................................................................................................... 63
4.2.1 Overview ........................................................................................................... 63
4.2.2 Reset Sequence.................................................................................................. 63
4.2.3 Interrupts after Reset.......................................................................................... 64
4.3 Interrupts ........................................................................................................................ 64
4.4 Trap Instruction .............................................................................................................. 65
4.5 Stack Status after Exception Handling ............................................................................ 66
4.6 Notes on Stack Usage ..................................................................................................... 66
Section 5 Interrupt Controller ........................................................................ 69
5.1 Overview ........................................................................................................................ 69
5.1.1 Features ............................................................................................................. 69
5.1.2 Block Diagram .................................................................................................. 70
5.1.3 Pin Configuration .............................................................................................. 71
5.1.4 Register Configuration....................................................................................... 71
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5.2 Register Descriptions ...................................................................................................... 72
5.2.1 System Control Register (SYSCR)..................................................................... 72
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................ 74
5.2.3 IRQ Status Register (ISR) .................................................................................. 79
5.2.4 IRQ Enable Register (IER) ................................................................................ 80
5.2.5 IRQ Sense Control Register (ISCR) ................................................................... 80
5.3 Interrupt Sources............................................................................................................. 81
5.3.1 External Interrupts ............................................................................................. 81
5.3.2 Internal Interrupts .............................................................................................. 82
5.3.3 Interrupt Vector Table ....................................................................................... 83
5.4 Interrupt Operation.......................................................................................................... 85
5.4.1 Interrupt Handling Process................................................................................. 85
5.4.2 Interrupt Sequence ............................................................................................. 91
5.4.3 Interrupt Response Time.................................................................................... 92
5.5 Usage Notes.................................................................................................................... 92
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 92
5.5.2 Instructions that Inhibit Interrupts ...................................................................... 93
5.5.3 Interrupts during EEPMOV Instruction Execution ............................................. 94
5.5.4 Usage Notes....................................................................................................... 94
Section 6 Bus Controller ................................................................................97
6.1 Overview ........................................................................................................................ 97
6.1.1 Features ............................................................................................................. 97
6.1.2 Block Diagram................................................................................................... 98
6.1.3 Input/Output Pins............................................................................................... 98
6.1.4 Register Configuration....................................................................................... 99
6.2 Register Descriptions ...................................................................................................... 99
6.2.1 Access State Control Register (ASTCR) ............................................................ 99
6.2.2 Wait Control Register (WCR)............................................................................ 100
6.2.3 Wait State Controller Enable Register (WCER) ................................................. 101
6.2.4 Address Control Register (ADRCR)................................................................... 102
6.3 Operation ........................................................................................................................ 104
6.3.1 Area Division..................................................................................................... 104
6.3.2 Bus Control Signal Timing ................................................................................ 106
6.3.3 Wait Modes ....................................................................................................... 108
6.3.4 Interconnections with Memory (Example) ......................................................... 114
6.4 Usage Notes.................................................................................................................... 116
6.4.1 Register Write Timing ....................................................................................... 116
6.4.2 Precautions on setting ASTCR and ABWCR* ................................................... 116
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