simultaneous sampling 12-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 70.6dB SNR and
88dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.3LSB
RMS
.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). The LVDS drivers have
optional internal termination and adjustable output levels
to ensure clean signal integrity.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n
n
n
n
n
n
n
n
2-Channel Simultaneous Sampling ADC
70.6dB SNR
88dB SFDR
Low Power: 292mW/238mW/200mW Total,
146mW/119mW/100mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
40-Pin (6mm
×
6mm) QFN Package
applicaTions
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V
V
DD
CH.1
ANALOG
INPUT
CH.2
ANALOG
INPUT
ENCODE
INPUT
12-BIT
ADC CORE
DATA
SERIALIZER
1.8V
OV
DD
OUT1A
AMPLITUDE (dBFS)
OUT1B
OUT2A
OUT2B
DATA
CLOCK
OUT
FRAME
GND
OGND
226812 TA01
LTC2268-12, 125Msps,
2-Tone FFT, f
IN
= 70MHz and 75MHz
0
–10
–20
–30
SERIALIZED
LVDS
OUTPUTS
–40
–50
–60
–70
–80
S/H
S/H
12-BIT
ADC CORE
PLL
–90
–100
–110
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
226812 TA01b
22687612fa
1
LTC2268-12/
LTC2267-12/LTC2266-12
absoluTe MaxiMuM raTings
(Note 1)
pin conFiguraTion
TOP VIEW
PAR/SER
OUT1A
+
–
Supply Voltages
V
DD
, OV
DD
................................................ –0.3V to 2V
Analog Input Voltage (A
IN+
, A
IN–
,
PAR/SER, SENSE) (Note 3) .............–0.3V to (V
DD
+0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
Digital Output Voltage .................. –0.3V to (OV
DD
+0.3V)
Operating Temperature Range
LTC2268C, 2267C, 2266C ........................ 0°C to 70°C
LTC2268I, 2267I, 2266I ....................... –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
40 39 38 37 36 35 34 33 32 31
A
IN1
+
OUT1A
–
30 OUT1B
+
29 OUT1B
–
28 DCO
+
27 DCO
–
26 OV
DD
25 OGND
24 FR
+
23 FR
–
22 OUT2A
+
21 OUT2A
–
OUT2B
+
SENSE
V
REF
GND
1
A
IN1–
2
V
CM1
3
REFH 4
REFH 5
REFL 6
REFL 7
V
CM2
8
A
IN2+
9
A
IN2–
10
11 12 13 14 15 16 17 18 19 20
V
DD
V
DD
ENC
+
–
41
GND
CS
SCK
SDI
ENC
GND
GND
SDO
V
DD
V
DD
UJ PACKAGE
40-LEAD (6mm
×
6mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 32°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC2268CUJ-12#PBF
LTC2268IUJ-12#PBF
LTC2267CUJ-12#PBF
LTC2267IUJ-12#PBF
LTC2266CUJ-12#PBF
LTC2266IUJ-12#PBF
TAPE AND REEL
LTC2268CUJ-12#TRPBF
LTC2268IUJ-12#TRPBF
LTC2267CUJ-12#TRPBF
LTC2267IUJ-12#TRPBF
LTC2266CUJ-12#TRPBF
LTC2266IUJ-12#TRPBF
PART MARKING*
LTC2268UJ-12
LTC2268UJ-12
LTC2267UJ-12
LTC2267UJ-12
LTC2266UJ-12
LTC2266UJ-12
PACKAGE DESCRIPTION
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
40-Lead (6mm
×
6mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
OUT2B
22687612fa
2
LTC2268-12/
LTC2267-12/LTC2266-12
converTer characTerisTics
PARAMETER
Resolution
(No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
External Reference
Internal Reference
External Reference
External Reference
Differential Analog Input
(Note 6)
Differential Analog Input
(Note 7)
Internal Reference
External Reference
CONDITIONS
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
LTC2268-12
MIN
12
–1
–0.5
–12
–2.4
±0.3
±0.1
±3
–0.9
–0.9
±20
±30
±10
±0.2
±3
0.3
1
0.5
12
0.6
TYP
MAX
MIN
12
–1
–0.4
–12
–2.4
±0.3
±0.1
±3
–0.9
–0.9
±20
±30
±10
±0.2
±3
0.3
1
0.4
12
0.6
LTC2267-12
TYP
MAX
MIN
12
–1
–0.4
–12
–2.4
±0.3
±0.1
±3
–0.9
–0.9
±20
±30
±10
±0.2
±3
0.3
1
0.4
12
0.6
LTC2266-12
TYP
MAX
UNITS
Bits
LSB
LSB
mV
%FS
%FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSB
RMS
analog inpuT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
External Reference Mode
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
0 < A
IN+
, A
IN–
< V
DD
0 < PAR/SER < V
DD
0.625 < SENSE < 1.3V
l
l
l
l
MIN
V
CM
– 100mV
0.625
TYP
1 to 2
V
CM
1.25
155
130
100
MAX
V
CM
+100mV
1.3
UNITS
V
P–P
V
V
µA
µA
µA
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
– A
IN–
)/2
External Voltage Reference Applied to SENSE
Analog Input Common Mode Current
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
l
l
l
–1
–3
–6
0
0.15
80
1
3
6
µA
µA
µA
ns
ps
RMS
dB
MHz
Figure 6 Test Circuit
800
22687612fa
3
LTC2268-12/
LTC2267-12/LTC2266-12
DigiTal accuracy
SYMBOL PARAMETER
SNR
Signal-to-Noise Ratio
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
LTC2268-12
CONDITIONS
5MHz Input
70MHz Input
140MHz Input
5MHz Input
70MHz Input
140MHz Input
5MHz Input
70MHz Input
140MHz Input
5MHz Input
70MHz Input
140MHz Input
10MHz Input
l
LTC2267-12
MIN
69.2
TYP
70.6
70.5
70.3
88
85
82
90
90
90
70.6
70.4
70
–105
MAX
LTC2266-12
MIN
69.4
TYP
70.6
70.5
70.3
88
85
82
90
90
90
70.4
70.3
69.9
–105
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
MIN
69.6
TYP
70.6
70.6
70.3
88
85
82
90
90
90
70.6
70.4
70
–105
MAX
SFDR
Spurious Free Dynamic Range
2
nd
or 3
rd
Harmonic
Spurious Free Dynamic Range
4
th
Harmonic or Higher
l
75
76
76
l
84
82
84
S/(N+D)
Signal-to-Noise Plus Distortion
Ratio
Crosstalk
l
69
68.8
69
inTernal reFerence characTerisTics
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400µA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600µA < I
OUT
< 1mA
I
OUT
= 0
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
MIN
0.5
•
V
DD
– 25mV
TYP
0.5
•
V
DD
±25
4
1.225
1.25
±25
7
0.6
1.275
MAX
0.V
DD
+ 25mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
DigiTal inpuTs anD ouTpuTs
SYMBOL PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
DIFFERENTIAL ENCODE MODE (ENC
–
NOT TIED TO GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
V
IN
R
IN
C
IN
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
V
DD
=1.8V
V
DD
=1.8V
ENC
+
to GND
(Note 8)
CONDITIONS
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
MIN
TYP
MAX
UNITS
l
l
l
0.2
1.1
0.2
10
3.5
1.2
1.6
3.6
V
V
V
V
kΩ
pF
V
0.6
V
V
kΩ
pF
22687612fa
Internally Set
Externally Set (Note 8)
ENC
+
, ENC
–
to GND
(See Figure 10)
SINGLE-ENDED ENCODE MODE (ENC
–
TIED TO GND)
l
l
l
1.2
0
30
3.5
3.6
(See Figure 11)
4
LTC2268-12/
LTC2267-12/LTC2266-12
DigiTal inpuTs anD ouTpuTs
SYMBOL PARAMETER
V
IH
V
IL
I
IN
C
IN
R
OL
I
OH
C
OUT
V
OD
V
OS
R
TERM
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
=1.8V
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
V
DD
=1.8V
V
DD
=1.8V
V
IN
= 0V to 3.6V
l
l
l
MIN
1.3
TYP
MAX
UNITS
V
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
0.6
–10
3
V
DD
=1.8V, SDO = 0V
SDO = 0V to 3.6V
l
V
µA
pF
Ω
10
SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
200
–10
3
247
125
1.125
1.125
350
175
1.25
1.25
100
454
250
1.375
1.375
10
µA
pF
mV
mV
V
V
Ω
DIGITAL DATA OUTPUTS
poWer reQuireMenTs
SYMBOL PARAMETER
V
DD
OV
DD
I
VDD
I
OVDD
P
DISS
P
SLEEP
P
NAP
CONDITIONS
Analog Supply Voltage (Note 10)
Output Supply Voltage (Note 10)
Analog Supply Current Sine Wave Input
Digital Supply Current
Power Dissipation
Sleep Mode Power
Nap Mode Power
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 9)
LTC2268-12
MIN
l
l
l
l
l
l
l
LTC2267-12
MIN
1.7
1.7
TYP
1.8
1.8
116
16
29
238
261
1
70
20
MAX
1.9
1.9
129
19
33
266
292
MIN
1.7
1.7
1.9
1.9
165
20
34
333
358
LTC2266-12
TYP
1.8
1.8
96
15
29
200
225
1
70
20
MAX
1.9
1.9
109
18
32
229
254
UNITS
V
V
mA
mA
mA
mW
mW
mW
mW
mW
TYP
1.8
1.8
146
16
30
292
317
1
70
20
MAX
1.7
1.7
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
P
DIFFCLK
Power Increase with Differential Encode Mode Enabled
(No Increase for Sleep Mode)
TiMing characTerisTics
SYMBOL PARAMETER
f
S
t
ENCL
t
ENCH
t
AP
Sampling Frequency
ENC Low Time (Note 8)
Analog Supply Current
Sample-and-Hold
Acquisition Delay Time
CONDITIONS
(Notes 10, 11)
The
l
denotes the specifications which apply over the full operating temperature
FLASH锁死了这是为什么，有没有办法解锁。为什么会有类似下面这几种报错：
Read status value 0x0001 from symbol PRG_status(24x系列)
ADC Calibration not complete, check if device is un ......
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
