Data Sheet
FEATURES
RF input frequency range: 17.5 GHz to 24 GHz
IF output frequency range: 2.5 GHz to 3.5 GHz
LO input frequency range: 7 GHz to 13.5 GHz
Conversion gain (with hybrid): 15 dB typical
SSB noise figure: 2.5 dB typical
Input IP3: 3 dBm typical
Input P1dB: −5 dBm typical
25 dB of image rejection
Single-ended, 50 Ω RF and LO input ports
Exposed pad, 4.9 mm × 4.9 mm, 32-terminal LCC
17.5 GHz to 24 GHz,
GaAs, MMIC, I/Q Downconverter
ADMV1012
FUNCTIONAL BLOCK DIAGRAM
VDRF VGRF
27
31
ADMV1012
RFIN
3
LOIN
10
VDLO
15
22
IF1
2
GND
4
GND
11
GND
16349-001
×2
20
IF2
Figure 1.
APPLICATIONS
Point to point microwave radios
Radars and electronic warfare systems
Instrumentation, automatic test equipment (ATE)
Satellite communications
GENERAL DESCRIPTION
The ADMV1012 is a compact, gallium arsenide (GaAs)
design, monolithic microwave integrated circuit (MMIC), in
phase/quadrature (I/Q) downconverter in a RoHS compliant
package optimized for point to point microwave radio designs
that operate in the 17.5 GHz to 24 GHz input frequency range.
The ADMV1012 provides 15 dB of conversion gain with 25 dB
of image rejection, and 2.5 dB noise figure. The ADMV1012
uses a radio frequency (RF) low noise amplifier (LNA) followed
by an I/Q, double balanced mixer, where a driver amplifier drives
the local oscillator (LO) with a ×2 multiplier. IF1 and IF2 mixer
quadrature outputs are provided, and an external 90° hybrid is
required to select the required sideband.
The I/Q mixer topology reduces the need for filtering of unwanted
sideband. The ADMV1012 is a much smaller alternative to
hybrid style, double sideband (DSB) downconverter assemblies
and eliminates the need for wire bonding by allowing the use of
surface-mount manufacturing assemblies.
The ADMV1012 downconverter comes in a compact, thermally
enhanced, 4.9 mm × 4.9 mm, 32-terminal LCC. The ADMV1012
operates over the −40°C to +85°C temperature range.
Rev. A
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ADMV1012
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Upper Sideband (Low-Side LO) ................................................. 6
Lower Sideband (High-Side LO) ................................................ 8
IF Bandwidth .............................................................................. 10
Leakage Performance ................................................................. 11
Data Sheet
Return Loss Performance .......................................................... 12
Spurious Performance ............................................................... 13
M × N Spurious Performance for LO = 0 dBm ...................... 13
Theory of Operation ...................................................................... 14
LO Driver Amplifier .................................................................. 14
Mixer ............................................................................................ 14
LNA .............................................................................................. 14
Applications Information .............................................................. 15
Typical Application Circuit ....................................................... 15
Evaluation Board Information ................................................. 16
Bill of Materials ........................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
2/2018—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
Figure 1 .............................................................................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Added Thermal Resistance Section and Table 3; Renumbered
Sequentially ....................................................................................... 4
Changes to Figure 2 and Table 4 ..................................................... 5
Changes to Figure 3 and Figure 6 ................................................... 6
Changes to Figure 12 ........................................................................ 7
Changes to Figure 24, Figure 25, and Figure 26 ......................... 10
Changes to Figure 27 through Figure 30 ..................................... 11
Changed M × N Spurious Performance for LO = 4 dBm Section
to M × N Spurious Performance for LO = 0 dBm Section ....... 13
Changes to M × N Spurious Performance for LO = 0 dBm
Section.............................................................................................. 13
Changes to LO Driver Amplifier Section .................................... 14
Changes to Applications Information Section and Figure 34........ 15
Changes to Power-On Sequence Section .................................... 16
Changes to Figure 37...................................................................... 17
Changes to Table 6.......................................................................... 18
Changes to Ordering Guide .......................................................... 19
10/2017—Revision 0: Initial Version
Rev. A | Page 2 of 19
Data Sheet
SPECIFICATIONS
ADMV1012
Data taken at VDRF = 3 V, VDLO = 3 V, LO = −4 dBm ≤ LO ≤ +4 dBm, −40°C ≤ T
A
≤ +85°C, with a Mini-Circuits® QCN-45+ power
splitter for both upper sideband (low-side LO) and lower sideband (high-side LO), unless otherwise noted.
Table 1.
Parameter
INPUT FREQUENCY RANGE
Radio Frequency
Local Oscillator
LO AMPLITUDE
OUTPUT FREQUENCY RANGE
Intermediate Frequency
RF PERFORMANCE
Conversion Gain
Single Sideband (SSB) Noise Figure
Lower Sideband (High-Side LO)
Upper Sideband (Low-Side LO)
Input Third-Order Intercept
Input 1 dB Compression Point
Image Rejection
Leakage
LO to RF
LO to IF
2× LO to IF
IM3 at Input
−20 dBm Input Power
−25 dBm Input Power
−30 dBm Input Power
Return Loss
RF Input
IF Output
LO Input
POWER INTERFACE
RF LNA Bias Voltage
LO Amplifier Bias Voltage
RF LNA Gate Voltage
RF Amplifier Bias Current
LO Amplifier Bias Current
RF Amplifier Gate Current
Total Power
Symbol
RF
LO
Test Conditions/Comments
Min
17.5
7
−4
2.5
With hybrid
10.5
SSB NF
2.1
2.5
3
−5
25
−37
−40
−40
−23 dBm per tone
−28 dBm per tone
−33 dBm per tone
46
52
56
52
60
70
−11
−23
−11
VDRF
VDLO
VGRF
IDRF
IDLO
IGRF
3
3
−1.8
Adjust VGRF between −1.8 V to −0.4 V to get IDRF
68
170
<1
0.7
−10
−10
−10
3.5
3.5
−0.4
3.5
4
dB
dB
dBm
dBm
dB
dBm
dBm
dBm
dBc
dBc
dBc
dB
dB
dB
V
V
mA
mA
mA
W
15
20
dB
Typ
Max
24
13.5
+4
3.5
Unit
GHz
GHz
dBm
GHz
0
IF
IP3
P1dB
At −20 dBm/tone
0
−9
20
−25
−25
−25
0.8
Rev. A | Page 3 of 19
ADMV1012
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
VDLO
VGRF
VDRF − VGRF
1
Input Power
RF
LO
Maximum Junction Temperature
Maximum Power Dissipation
Lifetime at Maximum Junction Temperature (T
J
)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
Moisture Sensitivity Level (MSL) Rating
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
1
Data Sheet
THERMAL RESISTANCE
Rating
4V
0V
6V
15 dBm
15 dBm
175°C
2W
>1 million hours
−40°C to +85°C
−65°C to +150°C
260°C
MSL3
750 V
500 V
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θ
JA
is thermal resistance, junction to ambient (°C/W), and θ
JC
is
thermal resistance, junction to case (°C/W).
Table 3. Thermal Resistance
Package Type
E-32-1
1
θ
JA1
33.4
θ
JC
34
Unit
°C/W
See JEDEC standard JESD51-2 for additional information on optimizing the
thermal impedance (PCB with 3 × 3 vias).
ESD CAUTION
The maximum VDRF voltage and the minimum VGRF voltage is determined
by this difference. If a maximum VDRF voltage of +4 V is required, then the
minimum VGRF voltage is −2 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 4 of 19
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32
31
30
29
28
27
26
25
NIC
VGRF
NIC
NIC
NIC
VDRF
NIC
NIC
ADMV1012
NIC
GND
RFIN
GND
NIC
NIC
NIC
NIC
1
2
3
4
5
6
7
8
ADMV1012
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
NIC
NIC
IF1
NIC
IF2
NIC
NIC
NIC
Figure
2.
Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 5 to 9, 12 to 14, 16 to 19,
21, 23 to 26, 28 to 30, 32
2, 4, 11
3
10
15
20, 22
27
31
Mnemonic
NIC
GND
RFIN
LOIN
VDLO
IF2, IF1
VDRF
VGRF
EPAD
Description
Not Internally Connected. It is recommended to ground these pins on the PCB.
Ground.
RF Input. This pin is ac-coupled internally and matched to 50 Ω single ended.
LO Input. This pin is ac-coupled internally and matched to 50 Ω single ended.
Power Supply Voltage for the LO Amplifier. Refer to the Applications Information section for the
required external components and biasing.
Quadrature IF Outputs. Matched to 50 Ω and ac coupled. No external dc block is required.
Power Supply Voltage for the RF Amplifier. Refer to the Applications Information section for the
required external components and biasing.
Power Supply Gate Voltage for the RF Amplifier. Refer to the Applications Information section for
the required external components and biasing.
Exposed Pad. The exposed pad must be connected to GND. Good RF and thermal grounding is
recommended.
Rev. A | Page 5 of 19
16349-002
NOTES
1. NIC = NOT INTERNALLY CONNECTED. IT IS
RECOMMENDED TO GROUND THESE PINS
ON THE PCB.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO GND. GOOD RF AND THERMAL
GROUNDING IS RECOMMENDED.
NIC
LOIN
GND
NIC
NIC
NIC
VDLO
NIC
9
10
11
12
13
14
15
16
嵌入式系统
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