Hitachi Single-Chip Microcomputer
H8/325 Series
H8/3257, H8/3256
H8/325, H8/324,
H8/323, H8/322
Hardware Manual
Preface
The H8/325 Series is a family of high-performance single-chip microcomputers ideally suited for
embedded control of industrial equipment. The chips are built around an H8/300 CPU core: a high-
speed processor. On-chip supporting modules provide ROM, RAM, two types of timers, I/O ports,
and a serial communication interface for easy implementation of compact, high-speed control
systems.
The H8/325 Series offers a selection of on-chip memory.
H8/3257: 60-kbyte ROM; 2-kbyte RAM
H8/3256: 48-kbyte ROM; 2-kbyte RAM
H8/325: 32-kbyte ROM; 1-kbyte RAM
H8/324: 24-kbyte ROM; 1-kbyte RAM
H8/323: 16-kbyte ROM; 512-byte RAM
H8/322: 8-kbyte ROM; 256-byte RAM
The H8/3257, H8/3256, H8/325, H8/323, and H8/322 chips are available with either electrically
programmable or mask-programmable ROM. Manufacturers can use the electrically programmable
ZTAT™ (Zero Turn-Around Time*) version to get production off to a fast start and make software
changes quickly, then switch over to the masked version for full-scale production runs.
This manual describes the H8/325 Series hardware. Refer to the
H8/300 Series Programming
Manual
for a detailed description of the instruction set.
* ZTAT is a registered trademark of Hitachi, Ltd.
CONTENTS
Section 1. Overview
............................................................................................................... 1
1.1
1.2
1.3
Overview...............................................................................................................................
Block Diagram......................................................................................................................
Pin Assignments and Functions............................................................................................
1.3.1 Pin Arrangement......................................................................................................
1.3.2 Pin Functions ...........................................................................................................
1
5
6
6
8
Section 2. MCU Operating Modes and Address Space
................................................ 15
2.1
2.2
2.3
Overview...............................................................................................................................
Mode Descriptions................................................................................................................
Address Space Map ..............................................................................................................
2.3.1 Access Speed ...........................................................................................................
2.3.2 IOS...........................................................................................................................
Mode and System Control Registers (MDCR and SYSCR).................................................
2.4.1 Mode Control Register (MDCR) – H’FFC5 ...........................................................
2.4.2 System Control Register (SYSCR) – H’FFC4 ........................................................
15
16
16
16
17
24
24
25
2.4
Section 3. CPU
........................................................................................................................ 27
3.1
3.2
Overview...............................................................................................................................
3.1.1 Features....................................................................................................................
Register Configuration..........................................................................................................
3.2.1 General Registers.....................................................................................................
3.2.2 Control Registers .....................................................................................................
3.2.3 Initial Register Values..............................................................................................
Addressing Modes ................................................................................................................
Data Formats.........................................................................................................................
3.4.1 Data Formats in General Registers..........................................................................
3.4.2 Memory Data Formats.............................................................................................
Instruction Set .......................................................................................................................
3.5.1 Data Transfer Instructions .......................................................................................
3.5.2 Arithmetic Operations .............................................................................................
3.5.3 Logic Operations .....................................................................................................
3.5.4 Shift Operations.......................................................................................................
3.5.5 Bit Manipulations ....................................................................................................
3.5.6 Branching Instructions.............................................................................................
3.5.7 System Control Instructions ....................................................................................
27
27
28
28
29
30
31
33
34
35
36
38
40
41
41
43
49
51
3.3
3.4
3.5
i
3.6
3.7
3.5.8 Block Data Transfer Instruction ..............................................................................
CPU States ............................................................................................................................
3.6.1 Program Execution State .........................................................................................
3.6.2 Exception-Handling State........................................................................................
3.6.3 Power-Down State ...................................................................................................
Access Timing and Bus Cycle ..............................................................................................
3.7.1 Access to On-Chip Memory (RAM and ROM) ......................................................
3.7.2 Access to On-Chip Register Field and External Devices ........................................
52
54
55
55
56
56
56
58
Section 4. Exception Handling
............................................................................................ 61
4.1
4.2
Overview...............................................................................................................................
Reset .....................................................................................................................................
4.2.1 Overview .................................................................................................................
4.2.2 Reset Sequence ........................................................................................................
4.2.3 Disabling of Interrupts after Reset...........................................................................
Interrupts...............................................................................................................................
4.3.1 Overview .................................................................................................................
4.3.2 Interrupt-Related Registers......................................................................................
4.3.3 External Interrupts ...................................................................................................
4.3.4 Internal Interrupts ....................................................................................................
4.3.5 Interrupt Handling ...................................................................................................
4.3.6 Interrupt Response Time..........................................................................................
Note on Stack Handling........................................................................................................
61
61
61
61
64
64
64
65
68
69
70
75
75
4.3
4.4
Section 5. I/O Ports
................................................................................................................ 77
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Overview............................................................................................................................... 77
Port 1..................................................................................................................................... 78
Port 2..................................................................................................................................... 81
Port 3..................................................................................................................................... 84
Port 4..................................................................................................................................... 87
Port 5..................................................................................................................................... 94
Port 6..................................................................................................................................... 99
Port 7..................................................................................................................................... 104
ii
Section 6. Parallel Handshaking Interface
....................................................................... 113
6.1
Overview............................................................................................................................... 113
6.1.1 Features.................................................................................................................... 113
6.1.2 Block Diagram......................................................................................................... 114
6.1.3 Input and Output Pins .............................................................................................. 115
6.1.4 Register Configuration ............................................................................................ 115
Register Descriptions............................................................................................................ 115
6.2.1 Port 3 Data Direction Register (P3DDR) ................................................................ 115
6.2.2 Port 3 Data Register (P3DR) ................................................................................... 116
6.2.3 Handshake Control/Status Register (HCSR)........................................................... 116
Operation .............................................................................................................................. 118
6.3.1 Output Timing of Output Strobe Signal .................................................................. 118
6.3.2 Busy Signal Output Timing ..................................................................................... 119
6.3.3 Operation in Software Standby Mode ..................................................................... 119
6.3.4 Sample Application ................................................................................................. 120
6.3.5 Interrupts.................................................................................................................. 121
6.2
6.3
Section 7. 16-Bit Free-Running Timer
.............................................................................. 123
7.1
Overview............................................................................................................................... 123
7.1.1 Features.................................................................................................................... 123
7.1.2 Block Diagram......................................................................................................... 123
7.1.3 Input and Output Pins .............................................................................................. 125
7.1.4 Register Configuration ............................................................................................ 125
Register Descriptions............................................................................................................ 126
7.2.1 Free-Running Counter (FRC) – H’FF92 ................................................................. 126
7.2.2 Output Compare Registers A and B
(OCRA and OCRB) – H’FF94 and H’FF96............................................................ 126
7.2.3 Input Capture Register (ICR) – H’FF98.................................................................. 127
7.2.4 Timer Control Register (TCR) – H’FF90................................................................ 128
7.2.5 Timer Control/Status Register (TCSR) – H’FF91................................................... 130
7.2.6 FRT Noise Canceler Control Register (FNCR) – H’FFFF...................................... 133
CPU Interface ....................................................................................................................... 133
Operation .............................................................................................................................. 136
7.4.1 FRC Incrementation Timing.................................................................................... 136
7.4.2 Output Compare Timing.......................................................................................... 138
7.4.3 FRC Clear Timing ................................................................................................... 138
7.4.4 Input Capture Timing .............................................................................................. 139
7.4.5 Timing of Input Capture Flag (ICF) Setting............................................................ 140
7.2
7.3
7.4
iii
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