DEMO MANUAL DC1337A
LTC2309
8-Channel, 12-Bit SAR ADC
with I
2
C Interface
Description
Demonstration circuit 1337A features the
LTC
®
2309,
a
low noise, low power, 8-channel, 12-bit, successive ap-
proximation ADC with an I
2
C compatible serial interface.
The LTC2309 is available in a 24-pin 4mm × 4mm QFN
package. DC1337A demonstrates the DC performance of
the LTC2309 in conjunction with the DC590 or DC2026
data collection boards (QuikEval™ controller). Alternatively,
by connecting the DC1337 into a customer application the
performance of the LTC2309 can be evaluated directly in
that circuit.
Design files for this circuit board are available at
http://www.linear.com/demo/DC1337A
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
QuikEval is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
BoarD photo
INPUTS
0V TO
REFCOMP
DC590 OR
DC2026
Figure 1. DC1337A Connection Diagram
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DEMO MANUAL DC1337A
Quick start proceDure
Connect the DC1337 to a QuikEval controller using the
supplied 14-conductor ribbon cable.
Make sure the
VCCIO jumper of the QuikEval controller is in the 5V
position.
Connect the QuikEval controller to a host PC with
a standard USB A/B cable. Apply an analog input voltage
to CH0-CH7 on connector J1. Run the evaluation software
supplied with the QuikEval controller or download it from
www.linear.com/software. The correct control panel will
be loaded automatically. Click the Collect (Figure 2) but-
ton to begin reading CH0-CH3. Press the Page 1 Button
to toggle to Page 2. This displays CH4-CH7. This button
toggles between the two displays.
The Help menu contains information on data logging the
ADC results. The Tools menu has the data logging option
as well as options for changing the number of points dis-
played, the number of points in an average and whether
the data is displayed in LSBs or Volts. The View menu can
be used to access the LTC2309 product page.
If the QuikEval program is started without the demo board
attached to the QuikEval controller, the Tools menu can be
used to check for updates and automatically install them.
DC1337 requires at least version K71 of the QuikEval
software.
harDware setup
Signal Connections
J1
Connector for CH0-CH7, COM and BIAS/2. Limit input
voltage swings to GND-VDD. For optimum performance, the
input should be bandlimited to the frequencies of interest.
Jumper J2
AD0 I
2
C address line. Set to GND for operation
with supplied software. For operation without QuikEval,
configure as desired: Low (GND), High (5V) or Float (FLT)
Jumper J3
AD1 I
2
C address line. Set to GND for operation
with supplied software. For operation without QuikEval,
configure as desired: Low (GND), High (5V) or Float (FLT)
Jumper J4
COM Common pin for single ended ADC
conversions. Can be set to GND or left floating (FLT) so
that COM can be driven by J1.
J5
QuikEval interface connector. Provides power and I2C
interface to the DC1337.
Jumper J6
BIAS Selects between REFCOMP and an
external bias voltage to drive the Bias/2 line. Bias/2 is
designed to set a center point for the minus input during
bipolar operation.
Turrets
EXT_BIAS
External Bias connection. This can be used
to drive the BIAS/2 line through a 2:1 divider. To use this
pin put jumper J6 in the EXT position and apply desired
bias voltage.
5V
5V supply line for the DC1337. Use this line only if the
QuikEval controller is not used
GND
Ground line for the DC1337
SDA
I
2
C bidirectional data line. Controlled by the QuikEval
controller if connected.
SCL
I
2
C clock line. Controlled by the QuikEval controller
if connected.
VREF
Connected to ADC V
REF
pin.
REFCOMP
Connected to ADC REFCOMP pin.
BIAS/2
Bias Voltage/2 (REFCOMP or EXT)
2
dc1337af
DEMO MANUAL DC1337A
harDware setup
Using the DC1337 without the QuikEval Controller
Interface signals SDA and SCL and power are normally
provided to the DC1337 by the QuikEval controller. If you
use this board without the QuikEval controller, it is the
user’s responsibility to connect a 5V power supply and
ground as well as generating SDA and SCL. These signals
can be provided through the 14-pin ribbon cable connector.
See schematic for pinout. See the LTC2309 data sheet for
information on driving SDA and SCL.
Figure 2. DC1337A QuikEval Screenshot
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DEMO MANUAL DC1337A
parts List
ITEM
1
QTY
3
REFERENCE
C1, C15, C16
PART DESCRIPTION
CAP 10µF, X5R, 6.3V, 20%, 0603
.,
MANUFACTURER/PART NUMBER
MURATA, GRM188R60J106ME47D AVX,
06036D106MAT2A NIC, NMC0603X5R106M6.3TRPF
TDK, C1608X5R0J106M080AB
AVX, 06033C104KAT2A TDK, C1608X7R1E104K080AA
AVX, 06033A470KAT2A
TAIYO YUDEN, JMK107BJ225KA-T AVX,
06036D225KAT2A MURATA, GRM188R60J225KE19D
TDK, C1608X7R1C105K080AC AVX, 0603YC105KAT2A
NIC, NMC0603X7R105K16TRPF
MILL-MAX, 2308-2-00-80-00-00-07-0
SAMTEC, TSW-110-07-L-D
SAMTEC, TSW-104-07-L-S
SAMTEC, TSW-103-07-L-S
MOLEX, 87831-1420
VISHAY, CRCW0603100RFKEA NIC, NRC06F1000TRF
VISHAY, CRCW060349R9FKEA PANASONIC,
ERJ3EKF49R9V
VISHAY, CRCW06034K99FKEA NIC, NRC06F4991TRF
LINEAR TECH., LTC2309CUF#PBF
MICROCHIP 24LC025-I/ST
,
SAMTEC, SNT-100-BK-G
DEMO CIRCUIT 1337A
STENCIL 1337A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
4
9
1
1
8
1
2
2
1
9
1
5
1
1
4
1
1
C2, C3 , C4, C18
C5, C6, C7, C8, C9,
C10, C11, C12, C13
C14
C17
E1, E2, E3, E4, E5,
E6, E7, E8
J1
J2, J3
J6, J4
J5
R1, R2, R3, R4, R5,
R6, R7, R8, R9
R10
R11, R12, R13, R14,
R15
U1
U2
JP2, JP3, JP4, JP6
CAP 0.1µF, X7R, 25V, 10%, 0603
.,
CAP
.,47pF, C0G, 25V, 10%, 0603
CAP 2.2µF, X5R, 6.3V, 10%, 0603
.,
CAP 1µF, X7R, 16V, 10%, 0603
.,
TEST POINT, TURRET, 0.064", MTG. HOLE
CONN., HDR., MALE, 2×10, 2.54mm, THT, STRT
CONN., HDR., MALE, 1×4, 2.54mm, THT, STRT
CONN., HDR., MALE, 1×3, 2.54mm, THT, STRT
CONN., HDR., MALE, 2×7, 2mm, THT, VERT,
SHROUDED
RES., 100Ω, 1%, 1/10W, 0603
RES., 49.9Ω, 1%, 1/10W, 0603
RES., 4.99kΩ, 1%, 1/10W, 0603
IC, 5V, 8-CH, 12-Bit I
2
C SAR ADC , QFN-24UF
IC, MEMORY, EEPROM, 2K-Bit, 400kHz, TSSOP-8
CONN., SHUNT, FEMALE, 2 POS, 2.54mm
PCB, DC1337A
STENCIL
4
dc1337af
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4
3
2
1
REVISION HISTORY
ECO
1
09/25/07
PROTO
This circuit is proprietary to Linear Technology and supplied
for use with Linear Technology parts.
Customer Notice:Linear
Technology has made a best effort to
design a circuit that meets customer-supplied specifications;
however, it remains the customer's responsibility to verify proper
and reliable operation in the actual application, Component
substitution and printed circuit board layout may significantly
affect circuit performance or reliability. Contact Linear
Applications Engineering for assistance.
REV
DESCRIPTION
DATE
APPROVED
D
5V
D
5V
5V
5V 5V
E1
C1
C4
U1
21
13
12
GND
10uF
0.1uF
C2
0.1uF
C3
0.1uF
E2
1
J1
2
R1
100
3
4
R2
100
LTC2309CUF
E3
VDD
VDD
VDD
5
6
R3
100
7
8
R4
100
schematic Diagram
9
10
R5
100
SDA
SCL
AD1
14
1
AD0
1
FLT
5V
GND
17
16
15
SDA
E4
SCL
11
12
R6
100
13
14
R7
100
VREF
REFCOMP
AD0
5V
AD1
FLT
5V
GND
GND
GND
GND
GND
GND
PAD
GND
15
9
8
10
11
18
19
20
25
7
2
3
4
3
4
2
16
R8
5V
100
22
23
24
1
2
3
4
5
6
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
J2
J3
17
18
R9
100
C
19
1
20
C
C5
47pF
GND
C6
47pF
C10
47pF
R10
E5
C14
BIAS
3
EXT
REFCOMP
C7
47pF
C11
47pF
49.9
1%
E7
C16
10uF
47pF
47pF
C12
C13
3
C8
47pF
2
FLT
J4
COM
C9
47pF
5V
VREF
1
2
J5
VUNREG
5V
2.2uF
REFCOMP
EXT_BIAS
C15
2
E6
1
J6
R11
6
4
7
5
11
10
9
CS
SCK/SCL
MOSI/SDA
MISO
EESCL
EEVCC
EESDA
B
10uF
4.99K
1%
R12
B
BIAS/2
E8
C17
1uF
1%
4.99K
R13
4.99K
1%
R14
4.99K
1%
8
6
SCL
U2
24LC025-I/ST
7
VCC
R15
4.99K
1%
12
14
EEGND
NC
GND
GND
3
3
2
1
FFGND
CONTRACT NO.
APPROVALS
DRAWN
CHECKED
APPROVED
ENGINEER
DESIGNER
mi
A2
A0
GND
A1
SDA
5
A
4
13
0.1uF
8
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
C18
WP
DATE
09/24/07
GND
TECHNOLOGY
TITLE
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
A
SCH, LTC2309CUF, 8-CH LOW NOISE I2C ADC
SIZE CAGE CODE
DWG NO
Tuesday, July 12, 2016
4
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