Low Skew, 1:18
Crystal-to-LVCMOS/LVTTL Fanout Buffer
Data Sheet
83918
General Description
The 83918 is a low skew, 1:18 Crystal-to- LVCMOS/LVTTL Fanout
Buffer. The 83918 has selectable LVCMOS/LVTTL clock or crystal
inputs. The low impedance LVCMOS/LVTTL outputs are designed to
drive 50 series or parallel terminated transmission lines.
The 83918 is characterized at full 3.3V, full 2.5V and mixed
3.3V/2.5V, 3.3V/1.8V, and 2.5V/1.8V output operating supply modes.
Guaranteed output and part-to-part skew characteristics make the
83918 ideal for those clock distribution applications demanding well
defined performance and repeatability.
Features
•
•
•
•
•
•
•
Eighteen LVCMOS/LVTTL output
Selectable crystal oscillator interface or LVCMOS_CLK
Maximum output frequency: 200MHz
Crystal input frequency range: 10MHz to 40MHz
RMS phase jitter using a 25MHz crystal (1kHz – 1MHz): 0.449ps
(typical) @ 3.3V/3.3V
Output skew: 75ps (maximum) @ 3.3V/3.3V
Operating supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
•
•
Block Diagram
CLK_SEL
Pulldown
XTAL_IN
Pin Assignment
V
DDO
GND
Q4
Q3
OSC
XTAL_OUT
0
18
32 31 30 29 28 27 26 25
GND
Q0:Q17
GND
LVCMOS_CLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
GND
V
DDO
Q17
Q16
Q15
Q14
Q13
Q12
Q0
Q2
Q5
Q1
24
23
22
21
20
19
18
17
Q6
Q7
Q8
V
DDO
Q9
Q10
Q11
GND
LVCMOS_CLK
Pulldown
1
CLK_SEL
XTAL_IN
XTAL_OUT
V
DD
V
DDO
83918
32 Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B March 17, 2016
83918 Data Sheet
Table 1. Pin Descriptions
Number
1, 2, 12, 17, 25
3
4
5,
6
7
8, 16, 21, 29
9, 10, 11,
13, 14, 15,
18, 19, 20, 22,
23, 24, 26, 27,
28, 30, 31, 32
Name
GND
LVCMOS_CLK
CLK_SEL
XTAL_IN,
XTAL_OUT
V
DD
V
DDO
Q17, Q16, Q15,
Q14, Q13, Q12,
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2,Q1, Q0
Power
Input
Input
Input
Power
Power
Pulldown
Pulldown
Type
Description
Power supply ground.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Clock select pin. When HIGH, selects LVCMOS_CLK. When LOW,
selects crystal inputs. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Positive supply pin.
Output supply pins.
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
V
DDO
= 3.465V
C
PD
Power Dissipation Capacitance
(per output)
V
DDO
= 2.625V
V
DDO
= 2V
R
PULLDOWN
Input Pulldown Resistor
V
DDO
= 3.465V
R
OUT
Output Impedance
V
DDO
= 2.625V
V
DDO
= 2V
18
20
25
Test Conditions
Minimum
Typical
4
9
8
8
51
19
22
29
20
24
34
Maximum
Units
pF
pF
pF
pF
k
©2016 Integrated Device Technology, Inc
2
Revision B March 17, 2016
83918 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
53.5C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
24
27
Units
V
V
mA
mA
Table 3B. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
24
26
Units
V
V
mA
mA
Table 3C. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
24
29
Units
V
V
mA
mA
©2016 Integrated Device Technology, Inc
3
Revision B March 17, 2016
83918 Data Sheet
Table 3D. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
23
25
Units
V
V
mA
mA
Table 3E. Power Supply DC Characteristics,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
Maximum
2.625
2.0
23
24
Units
V
V
mA
mA
Table 3F. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
CLK_SEL,
LVCMOS_CLK
CLK_SEL,
LVCMOS_CLK
Test Conditions
V
DD
= 3.465V
V
DD
= 2.5V
V
DD
= 3.465V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.465V
V
OH
Output High Voltage
V
DDO
= 2.625V
V
DDO
= 2V
V
OL
Output Low Voltage
V
DDO
= 3.465 or 2.625V
V
DDO
= 2V
-5
2.6
1.8
V
DDO
– 0.3
0.5
0.35
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
V
V
V
V
V
IL
I
IH
I
IL
NOTE 1: Outputs terminated with 50
to V
DDO
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
10
Test Conditions
Minimum
Typical
Fundamental
40
50
7
MHz
Maximum
Units
pF
©2016 Integrated Device Technology, Inc
4
Revision B March 17, 2016
83918 Data Sheet
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
tp
LH
tjit(Ø)
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay, Low to High;
NOTE 1
RMS Phase Jitter, (Random);
NOTE 2
Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
Output Skew; NOTE 3, 6
Part-to-Part Skew; NOTE 4, 6
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
20% to 80%
ƒ
OUT
150MHz
300
45
25MHz,
Integration Range: 1kHz to 1MHz
155.52MHz,
Integration Range: 12kHz to 20MHz
1.85
0.449
0.145
75
800
700
55
Test Conditions
Minimum
Typical
Maximum
200
3.0
Units
MHz
ns
ps
ps
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f
OUT
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
5
Revision B March 17, 2016
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