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74HCT4046ADB,118: 产品描述IC PLL W/VCO 16SSOP; 产品类别模拟混合信号IC 信号电路; 文件大小1MB，共50页; 制造商Nexperia; 官网地址https://www.nexperia.com; 标准

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74HCT4046ADB,118概述

IC PLL W/VCO 16SSOP

74HCT4046ADB,118规格参数

参数名称	属性值
Brand Name	Nexperia
是否Rohs认证	符合
厂商名称	Nexperia
零件包装代码	SSOP1
包装说明	SSOP-16
针数	16
制造商包装代码	SOT338-1
Reach Compliance Code	compliant
Samacsys Description	74HC(T)4046A - Phase-locked-loop with VCO@en-us
模拟集成电路 - 其他类型	PLL FREQUENCY SYNTHESIZER
JESD-30 代码	R-PDSO-G16
JESD-609代码	e4
长度	6.2 mm
湿度敏感等级	1
功能数量	1
端子数量	16
最高工作温度	125 °C
最低工作温度	-40 °C
封装主体材料	PLASTIC/EPOXY
封装代码	SSOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	260
认证状态	Not Qualified
座面最大高度	2 mm
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	AUTOMOTIVE
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING
端子节距	0.65 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	5.3 mm

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74HC4046A; 74HCT4046A

Phase-locked loop with VCO

Rev. 3 — 8 June 2016

Product data sheet

1. General description

The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in

compliance with JEDEC standard no 7A.

2. Features and benefits



Low power consumption

VCO-Inhibit control for ON/OFF keying and for low standby power consumption

Center frequency up to 17 MHz (typical) at V

= 4.5 V

Choice of three phase comparators:



PC1: EXCLUSIVE-OR



PC2: Edge-triggered J-K flip-flop



PC3: Edge-triggered RS flip-flop

Excellent Voltage Controlled Oscillator (VCO) linearity

Low frequency drift with supply voltage and temperature variations

Operating power supply voltage range:



VCO section 3.0 V to 6.0 V



Digital section 2.0 V to 6.0 V

Zero voltage offset due to operational amplifier buffering

ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



3. Applications



FM modulation and demodulation

Frequency synthesis and multiplication

Frequency discrimination

Tone decoding

Data synchronization and conditioning

Voltage-to-frequency conversion

Motor-speed control

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

8. Functional description

The 74HC4046A; 74HCT4046A is a phase-locked-loop circuit that comprises a linear

voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and

PC3). It has a common signal input amplifier and a common comparator input (see

Figure 1).

The signal input can be directly coupled to a large voltage signal, or indirectly

coupled (with a series capacitor) to a small voltage signal. A self-bias input circuit keeps

small voltage signals within the linear region of the input amplifiers. With a passive

low-pass filter, the 74HC4046A; 74HCT4046A forms a second-order loop PLL. The

excellent VCO linearity is achieved by the use of linear op amp techniques.

8.1 VCO

The VCO requires one external capacitor C1 (between pins C1A and C1B) and one

external resistor R1 (between pins R1 and GND). Alternatively, it requires two external

resistors R1 and R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and

capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to

have a frequency offset if necessary (see

Figure 4).

The high input impedance of the VCO simplifies the design of the low-pass filters by giving

the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass

filter, a demodulator output of the VCO input voltage is provided at pin DEM_OUT. In

contrast to conventional techniques, where the DEM_OUT voltage is one threshold

voltage lower than the VCO input voltage, the DEM_OUT voltage equals the VCO input. If

DEM_OUT is used, a series resistor (R

) should be connected from pin DEM_OUT to

GND; if unused, DEM_OUT should be left open. The VCO output (pin VCO_OUT) can be

connected directly to the comparator input (pin COMP_IN), or connected via a frequency

divider. When the VCO input DC level is held constant, the VCO output signal has a duty

cycle of 50 % (maximum expected deviation 1 %). A LOW-level at the inhibit input

(pin INH) enables the VCO and demodulator, while a HIGH-level turns both off to

minimize standby power consumption.

The only difference between the 74HC4046A and 74HCT4046A is the input level

specification of the INH input. This input disables the VCO section. The sections of the

comparator are identical, so that there is no difference in the SIG_IN or COMP_IN inputs

between the 74HC4046A and 74HCT4046A.

8.2 Phase comparators

The input signal can be coupled to the self-biasing amplifier at pin SIG_IN, when the

signal swing is between the standard HC family input logic levels. Capacitive coupling is

required for signals with smaller swings.

74HC_HCT4046A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 8 June 2016

5 of 50

74HCT4046ADB,118相似产品对比

	74HCT4046ADB,118	74HCT4046AD,112	74HC4046APW,118	74HC4046ADB,118	74HC4046ADB,112	74HCT4046ADB,112
描述	IC PLL W/VCO 16SSOP	IC PHASE LOCK LOOP W/VCO 16SOIC	IC PHASE LOCK LOOP W/VCO 16TSSOP	IC PHASE LOCK LOOP W/VCO 16SSOP	IC PLL W/VCO 16-SSOP	IC PLL W/VCO 16-SSOP
Brand Name	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia
零件包装代码	SSOP1	SOP	TSSOP	SSOP1	SSOP1	SSOP1
包装说明	SSOP-16	SOP-16	TSSOP,	SSOP-16	SSOP-16	SSOP-16
针数	16	16	16	16	16	16
制造商包装代码	SOT338-1	SOT109-1	SOT403-1	SOT338-1	SOT338-1	SOT338-1
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
模拟集成电路 - 其他类型	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER	PLL FREQUENCY SYNTHESIZER
JESD-30 代码	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
JESD-609代码	e4	e4	e4	e4	e4	e4
长度	6.2 mm	9.9 mm	5 mm	6.2 mm	6.2 mm	6.2 mm
湿度敏感等级	1	1	1	1	1	1
功能数量	1	1	1	1	1	1
端子数量	16	16	16	16	16	16
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	SSOP	SOP	TSSOP	SSOP	SSOP	SSOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）	260	260	260	260	260	260
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	2 mm	1.75 mm	1.1 mm	2 mm	2 mm	2 mm
最大供电电压 (Vsup)	5.5 V	5.5 V	6 V	6 V	6 V	5.5 V
最小供电电压 (Vsup)	4.5 V	4.5 V	2 V	2 V	2 V	4.5 V
标称供电电压 (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	1.27 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30	30	30	30
宽度	5.3 mm	3.81 mm	4.4 mm	5.3 mm	5.3 mm	5.3 mm
是否Rohs认证	符合	符合	-	符合	符合	符合
厂商名称	Nexperia	Nexperia	-	Nexperia	Nexperia	Nexperia

74HCT4046ADB,118

74HCT4046ADB,118概述

74HCT4046ADB,118规格参数

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