74LVC1G98
Low-power configurable multiple function gate
Rev. 4 — 19 December 2016
Product data sheet
1. General description
The 74LVC1G98 is a configurable multiple function gate with Schmitt-trigger inputs. The
device can be configured as any of the following logic functions MUX, AND, OR, NAND,
NOR, inverter and buffer; using the 3-bit input. All inputs can be connected to V
CC
or
GND.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V environments.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
24
mA output drive (V
CC
= 3.0 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C.
Nexperia
74LVC1G98
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC1G98GW
74LVC1G98GV
74LVC1G98GM
74LVC1G98GF
74LVC1G98GN
74LVC1G98GS
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SC-88
SC-74
XSON6
XSON6
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
plastic surface mounted package; 6 leads
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
Version
SOT363
SOT457
SOT886
SOT891
SOT1115
SOT1202
Type number
4. Marking
Table 2.
Marking
Marking code
[1]
V9
V98
V9
V9
V9
V9
Type number
74LVC1G98GW
74LVC1G98GV
74LVC1G98GM
74LVC1G98GF
74LVC1G98GN
74LVC1G98GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1.
Logic symbol
74LVC1G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 19 December 2016
2 of 20
Nexperia
74LVC1G98
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
Fig 2.
Pin configuration SOT363
and SOT457
Fig 3.
Pin configuration SOT886
Fig 4.
Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
H
H
L
L
H
L
H
L
H = HIGH voltage level; L = LOW voltage level.
74LVC1G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 19 December 2016
3 of 20
Nexperia
74LVC1G98
Low-power configurable multiple function gate
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 5
see
Figure 6
see
Figure 7
see
Figure 7
see
Figure 8
see
Figure 8
see
Figure 9
see
Figure 10
see
Figure 11
Logic function
2-input MUX with inverted output
2-input NAND
2-input NOR with one input inverted
2-input AND with one input inverted
2-input NAND with one input inverted
2-input OR with one input inverted
2-input NOR
Buffer
Inverter
Fig 5.
2-input MUX with inverted output
Fig 6.
2-input NAND gate
Fig 7.
2-input AND gate with input A inverted or
2-input NOR gate with inverted C input
Fig 8.
2-input OR gate with input B inverted or
2-input NAND gate with input C inverted
Fig 9.
2-input NOR gate
Fig 10. Buffer
74LVC1G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 19 December 2016
4 of 20
Nexperia
74LVC1G98
Low-power configurable multiple function gate
Fig 11. Inverter
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
50
+6.5
+6.5
50
+100
-
+150
250
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For SC-88 and SC-74 packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 118
C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Active mode
V
CC
= 0 V; Power-down mode
Conditions
Min
1.65
0
0
0
40
Typ
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
Unit
V
V
V
V
C
74LVC1G98
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 4 — 19 December 2016
5 of 20
嵌入式系统
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