FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler
November 2010
FOD8012
High CMR, Bi-Directional, Logic Gate Optocoupler
Features
■
Full Duplex, Bi-Directional
■
20kV/µs Minimum Common Mode Rejection
■
High Speed:
Description
The FOD8012 is a full duplex, bi-directional, high-speed
logic gate Optocoupler, which supports isolated commu-
nications allowing digital signals to communicate
between systems without conducting ground loops or
hazardous voltages. It utilizes Fairchild’s
proprietary
co
-
,
pla
nar packaging technology, Optoplanar
®
and opti
-
IC design to achieve minimum 20kV/µs Common Mode
Noise Rejection (CMR) rating.
This high-speed logic gate optocoupler is highly inte-
grated with 2 optically coupled channels arranged in
bi-directional configuration, and housed in a compact
8-pin small outline package. Each optocoupler channel
consists of a high-speed AlGaAs LED driven by a CMOS
buffer IC coupled to a CMOS detector IC. The detector
IC comprises of an integrated photodiode, a high-speed
trans-impedance amplifier and a voltage comparator
with an output driver. The CMOS technology coupled to
the high efficiency of the LED achieves low power con-
sumption as well as very high speed (60ns propagation
delay, 15ns pulse width distortion).
– 15Mbit/sec Data Rate (NRZ)
– 60ns max. Propagation Delay
– 15ns max. Pulse Width Distortion
– 30ns max. Propagation Delay Skew
■
3.3V and 5V CMOS Compatibility
■
Extended industrial temperate range, -40 to +110˚C
temperature range
■
Safety and regulatory approvals
– UL1577, 3750 VAC
RMS
for 1 min.
– DIN EN/IEC60747-5-2 (approval pending)
Applications
■
Industrial fieldbus communications
– DeviceNet, CAN, RS485, RS232
■
Microprocessor System Interface
– SPI, I
2
C
■
Programmable Logic Control
■
Isolated Data Acquisition System
■
Voltage Level Translator
Related Resources
■
FOD8001, High Noise Immunity, 3.3V/5V Logic Gate
Optocoupler Datasheet
■
www.fairchildsemi.com/products/opto/
Functional Schematic
V
DD1
V
OA
1
8
V
DD2
Truth Table
2
7
V
INA
VIN
High
Low
LED
OFF
ON
VO
High
Low
V
INB
GND
1
3
6
V
OB
GND
2
4
5
0.1µF bypass capacitor required from V
DD
to GND
©2010 Fairchild Semiconductor Corporation
FOD8012 Rev. 1.0.5
www.fairchildsemi.com
FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler
Pin Definitions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
V
DD1
V
OA
V
INB
GND
1
GND
2
V
OB
V
INA
V
DD2
Description
Supply Voltage
to Channel-A detector IC and Channel-B buffer IC
Output Voltage
from Channel-A detector IC
Input Voltage
to Channel-B buffer IC
Ground
for Channel-A detector IC and Channel-B buffer IC
Ground
for Channel-A buffer IC and Channel-B detector IC
Output Voltage
from Channel-B detector IC
Input Voltage
to Channel-A buffer IC
Supply Voltage
to Channel-A buffer IC and Channel-B detector IC
Absolute Maximum Ratings
(T
A
=25ºC unless otherwise specified)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
T
STG
T
OPR
T
J
T
SOL
V
DD1
, V
DD2
V
IA
, V
IB
I
IA
, I
IB
V
OA
, V
OB
I
OA
, I
OB
PD
I
PD
O
Parameter
Storage Temperature
Operating Temperature
Junction Temperature
Lead Solder Temperature
(Refer to Reflow Temperature Profile)
Supply Voltage
Input Voltage
Input DC Current
Output Voltage
Average Output Current
Input Power Dissipation
(1)
Output Power Dissipation
(1)
Value
-40 to +125
-40 to +110
-40 to +130
260 for 10sec
0 to 6.0
-0.5 to VDD+0.5
-10 to +10
-0.5 to VDD+0.5
10
60
60
Units
ºC
ºC
ºC
ºC
V
V
µA
V
mA
mW
mW
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
T
A
V
DD1
, V
DD2
V
IH
V
IL
t
r
, t
f
Parameter
Ambient Operating Temperature
Supply Voltages (3.3V Operation)
(2)
Supply Voltages (5.0V Operation)
(2)
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Time
Min.
-40
3.0
4.5
2.0
0
Max.
+110
3.6
5.5
V
DD
0.8
1.0
Unit
ºC
V
V
V
V
ms
©2010 Fairchild Semiconductor Corporation
FOD8012 Rev. 1.0.5
www.fairchildsemi.com
2
FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler
Isolation Characteristics
Apply over all recommended conditions, typical value is measured at T
A
= 25ºC
Symbol
V
ISO
R
ISO
C
ISO
Parameter
Input-Output Isolation Voltage
Isolation Resistance
Isolation Capacitance
Conditions
freq = 60Hz, t = 1.0min,
I
I-O
≤
10µA
(3)(4)
V
I-O
= 500V
(3)
V
I-O
= 0V, freq = 1.0MHz
(3)
Min.
3750
10
11
Typ.
Max.
Units
Vac
RMS
Ω
0.2
pF
Electrical Characteristics
T
A
= -40ºC to +110ºC, 3.0V
≤
V
DD
≤
5.5V, unless otherwise specified.
Apply over all recommended conditions, typical value is measured at V
DD1
= V
DD2
= +3.3V, T
A
= 25ºC
Symbol
I
DD1L
, I
DD2L
I
DD1H
, I
DD2H
I
IA
, I
IB
V
OH
Parameter
Logic Low Supply Current
Input Current
Conditions
V
IA
, V
IB
= 0V
Min.
Typ.
5.8
2.5
Max.
8.0
4.0
+10
Units
mA
mA
µA
V
V
V
V
Logic High Supply Current V
IA
, V
IB
= V
DD
-10
3.2
3.0
4.9
4.7
Logic High Output Voltage I
O
= –20µA, V
DD
= 3.3V, V
I
= V
IH
I
O
= –4mA, V
DD
= 3.3V, V
I
= V
IH
I
O
= –20µA, V
DD
= 5V, V
I
= V
IH
I
O
= –4mA, V
DD
= 5V, V
I
= V
IH
3.3
3.1
5.0
4.8
0
0.26
0.1
0.6
V
OL
Logic Low Output Voltage
I
O
= 20µA, V
DD
= 3.3V or 5V,
V
I
= V
IL
I
O
= 4mA, V
DD
= 3.3V or 5V,
V
I
= V
IL
V
V
©2010 Fairchild Semiconductor Corporation
FOD8012 Rev. 1.0.5
www.fairchildsemi.com
3
FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler
Switching Characteristics
T
A
= -40ºC to +110ºC, 3.0V
≤
V
DD
≤
5.5V, unless otherwise specified.
Apply over all recommended conditions, typical value is measured at V
DD1
= V
DD2
= +3.3V, T
A
=25ºC
Symbol
Data Rate
t
PHL
t
PLH
PWD
t
PSK(CC)
t
PSK(PP)
t
R
t
F
|CM
H
|
|CM
L
|
Parameter
Conditions
Min.
Typ.
Max.
15
Units
Mbit/s
ns
ns
ns
ns
ns
ns
ns
kV/µs
kV/µs
Propagation Delay Time
to Logic Low Output
Propagation Delay Time
to Logic High Output
Pulse Width Distortion,
| t
PHL
– t
PLH
|
Channel-Channel Skew
Part-Part Skew
Output Rise Time
(10% to 90%)
Output Fall Time
(90% to 10%)
Common Mode Transient
Immunity at Output High
Common Mode Transient
Immunity at Output Low
PW = 66.7ns, C
L
= 15pF
PW = 66.7ns, C
L
= 15pF
PW = 66.7ns, C
L
= 15pF
(5)
PW = 66.7ns, C
L
= 15pF
(6)
PW = 66.7ns, C
L
= 15pF
(7)
PW = 66.7ns, C
L
= 15pF
PW = 66.7ns, C
L
= 15pF
V
I
= V
DD1
, V
O
> 0.8V
DD1
,
V
CM
= 1000V
(8)
V
I
= 0V, V
O
< 0.8V,
V
CM
= 1000V
(8)
20
20
37
40
3
12
60
60
15
25
30
6.5
6.5
40
40
Notes:
1. No derating required.
2. 0.1µF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. The capacitors should be kept close
to the supply pins.
3. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
4. 3,750 VAC
RMS
for 1 minute duration is equivalent to 4,500 VAC
RMS
for 1 second duration.
5. PWD is equal to the magnitude of the worst case difference in t
PHL
and/or t
PLH
that will be seen for one channel
switching, while holding the other channel output at a low or high state, or while both channels are in synchronous
data transmission mode.
6. t
PSK(CC)
is equal to the magnitude of the worst case difference in t
PHL
and/or t
PLH
that will be seen between the two
channels within a single device.
7. t
PSK(PP)
is equal to the magnitude of the worst case difference in t
PHL
and/or t
PLH
that will be seen between any two
units from the same manufacturing date code that are operated at same case temperature, at same operating
conditions, with equal loads.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient
immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal,
Vcm, to assure that the output will remain low.
©2010 Fairchild Semiconductor Corporation
FOD8012 Rev. 1.0.5
www.fairchildsemi.com
4
FOD8012 — High CMR, Bi-Directional, Logic Gate Optocoupler
Typical Performance Curves
Fig. 1 Typical Output Voltage vs. Input Voltage
(Channel A & B)
4.0
2.0
Fig. 2 Typical Input Voltage Switching Threshold
vs. Input Supply Voltage (Channel A & B)
V
DD1
= V
DD1
= 3.3V
V
ITH
–
INPUT VOLTAGE SWITCHING
THRESHOLD (V)
0
1
2
3
4
5
V
O
–
OUTPUT VOLTAGE (V)
1.8
3.0
1.6
2.0
1.4
1.0
1.2
0
1.0
3.0
3.5
4.0
4.5
5.0
5.5
V
I
–
INPUT VOLTAGE (V)
V
DD
–
SUPPLY VOLTAGE (V)
Fig. 3 Typical Propagation Delay vs.
Ambient Temperature (Channel A & B)
54
Fig. 4 Typical t
PHL
– t
PLH
vs. Ambient Temperature
(Channel A & B)
2
1
0
t
P
– PROPAGATION DELAY (ns)
50
Frequency = 7.5MHz
Duty Cycle = 50%
V
DD1
= V
DD2
= 3.3V
Frequency = 7.5MHz
Duty Cycle = 50%
V
DD1
= V
DD2
= 3.3V
46
t
PHL
– t
PLH
(ns)
t
PHL
40
60
80
100 110
-1
-2
-3
-4
42
t
PLH
38
34
-5
30
-40
-6
-40
-20
0
20
-20
0
20
40
60
80
100 110
T
A
–
AMBIENT TEMPERATURE (°C)
T
A
–
AMBIENT TEMPERATURE (°C)
Fig. 5 Typical Rise Time vs. Ambient Temperature
(Channel A & B)
7.0
Fig. 6 Typical Fall Time vs. Ambient Temperature
(Channel A & B)
9.0
8.5
8.0
6.5
Frequency = 7.5MHz
Duty Cycle = 50%
V
DD1
= V
DD2
= 3.3V
Frequency = 7.5MHz
Duty Cycle = 50%
V
DD1
= V
DD2
= 3.3V
t
R
– RISE TIME (ns)
6.0
t
F
– FALL TIME (ns)
t
R
5.5
7.5
7.0
t
F
6.5
6.0
5.0
4.5
5.5
4.0
-40
5.0
-40
-20
0
20
40
60
80
100 110
-20
0
20
40
60
80
100 110
T
A
–
AMBIENT TEMPERATURE (°C)
T
A
–
AMBIENT TEMPERATURE (°C)
©2010 Fairchild Semiconductor Corporation
FOD8012 Rev. 1.0.5
www.fairchildsemi.com
5
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