2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
Features
DDR2 SDRAM SORDIMM
MT18HTS25672RHZ – 2GB
Features
•
200-pin, small-outline registered dual in-line memo-
ry module (SORDIMM)
•
Fast data transfer rates: PC2-4200, PC2-5300, or
PC2-6400
•
2GB (256 Meg x 72)
•
Supports ECC error detection and correction
•
V
DD
= 1.8V
•
V
DDSPD
= 3.0–3.6V
•
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
•
Differential data strobe (DQS, DQS#) option
•
4n-bit prefetch architecture
•
Multiple internal device banks for concurrent opera-
tion
•
Programmable CAS latency (CL)
•
Posted CAS additive latency (AL)
•
WRITE latency = READ latency - 1
t
CK
•
Programmable burst lengths (BL): 4 or 8
•
Adjustable data-output drive strength
•
64ms, 8192-cycle refresh
•
On-die termination (ODT)
•
Serial presence detect (SPD) with EEPROM
•
Phase-lock loop (PLL) to reduce system clock line
loading
•
Gold edge contacts
•
Dual rank, using 2Gb TwinDie™ devices
•
Halogen-free
•
Combination Temp Sensor/EEPROM
Table 1: Key Timing Parameters
Speed
Grade
-80E
-800
-667
-53E
-40E
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 6
800
800
–
–
–
CL = 5
800
667
667
–
–
CL = 4
533
533
553
553
400
CL = 3
400
400
400
400
400
t
RCD
t
RP
t
RC
Figure 1: 200-Pin SORDIMM (R/C B)
Module height: 30mm (1.181 in)
Options
•
Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
1
•
Package
–
200-pin DIMM (Halogen-free)
•
Frequency/CL
2
–
2.5 @ CL = 5 (DDR2-800)
–
2.5 @ CL = 6 (DDR2-800)
–
3.0ns @ CL = 5 (DDR2-667)
Notes:
Marking
None
I
Z
-80E
-800
-667
1. Contact Micron for industrial temperature
module offerings
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
(ns)
12.5
15
15
15
15
(ns)
12.5
15
15
15
15
(ns)
55
55
55
55
55
PDF: 09005aef83f287c1
hts18c256x72rhz.pdf - Rev. A 3/10 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
1GB
8K
16K A[13:0]
8 BA[2:0]
2Gb TwinDie (256 Meg x 8)
1K A[9:0]
2 S#[1:0]
Table 3: Part Numbers and Timing Parameters – 2GB Modules
Base device: MT47H256M8,
1
2Gb DDR2 TwinDie SDRAM
Module
2
Part Number
Density
Configuration
MT18HTS25672RH(I)Z-80E__
MT18HTS25672RH(I)Z-800__
MT18HTS25672RH(I)Z-667__
Notes:
2GB
2GB
2GB
256 Meg x 72
256Meg x 72
256 Meg x 72
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT18HTS25672RHZ-80EG1.
PDF: 09005aef83f287c1
hts18c256x72rhz.pdf - Rev. A 3/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
Pin Assignments
Pin Assignments
Table 4: Pin Assignments
200-Pin SORDIMM Front
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Symbol
V
REF
DQ0
V
SS
DQ1
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Symbol
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CKE0
CKE1
EVENT#
V
DD
A12
A9
A7
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Symbol
V
DD
A5
A3
A2
V
DD
A10
BA0
RAS#
V
DD
CAS#
S1#
V
DD
ODT1
NC
DQ32
V
SS
DQ33
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
Pin
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Symbol
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
DQ58
V
SS
DQ59
V
DDSPD
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Symbol
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
RESET#
DM2
V
SS
DQ22
DQ23
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
200-Pin SORDIMM Back
Symbol
V
SS
DQ28
DQ29
V
SS
DM3
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8
V
SS
CB6
CB7
V
SS
CB2
CB3
V
SS
BA2
NC
A11
V
DD
A8
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Symbol
A6
A4
V
DD
A1
A0
BA1
V
DD
WE#
S0#
ODT0
A13
V
DD
CK0
CK0#
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
Pin
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Symbol
V
SS
DM5
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DM7
DQ62
V
SS
DQ63
SDA
SCL
SA1
SA0
PDF: 09005aef83f287c1
hts18c256x72rhz.pdf - Rev. A 3/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 5: Pin Descriptions
Symbol
Ax
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs:
Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
Clock:
Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable:
Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
Data mask (x8 devices only):
DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination:
Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select:
Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
Used to configure the SPD EEPROM address range on the I
2
C
bus.
Serial clock for SPD EEPROM:
Used to synchronize communication to and from the
SPD EEPROM on the I
2
C bus.
Check bits.
Used for system error detection and correction.
Data input/output:
Bidirectional data bus.
Data strobe:
Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
BAx
Input
CKx,
CK#x
CKEx
DMx,
Input
Input
Input
ODTx
Input
Par_In
RAS#, CAS#, WE#
RESET#
S#x
SAx
SCL
CBx
DQx
DQSx,
DQS#x
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
PDF: 09005aef83f287c1
hts18c256x72rhz.pdf - Rev. A 3/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol
SDA
RDQSx,
RDQS#x
Type
I/O
Output
Description
Serial data:
Used to transfer addresses and data into and out of the SPD EEPROM on
the I
2
C bus.
Redundant data strobe (x8 devices only):
RDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disa-
bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Err_Out#
V
DD
/V
DDQ
V
DDSPD
V
REF
V
SS
NC
NF
NU
RFU
Output
Parity error output:
Parity error found on the command and address bus.
(open drain)
Supply
Supply
Supply
Supply
–
–
–
–
Power supply:
1.8V ±0.1V. The component V
DD
and V
DDQ
are connected to the mod-
ule V
DD
.
SPD EEPROM power supply:
1.7–3.6V.
Reference voltage:
V
DD
/2.
Ground.
No connect:
These pins are not connected on the module.
No function:
These pins are connected within the module, but provide no functionality.
Not used:
These pins are not used in specific module configurations/operations.
Reserved for future use.
PDF: 09005aef83f287c1
hts18c256x72rhz.pdf - Rev. A 3/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2010 Micron Technology, Inc. All rights reserved.
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