1GB, 2GB (x64, SR): 240-Pin DDR3 SDRAM UDIMM
Features
DDR3 SDRAM UDIMM
MT8JTF12864A – 1GB
MT8JTF25664A – 2GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as
defined in the component data sheet
• 240-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC3-12800, PC3-10600
PC3-8500 or PC3-6400
• 1GB (128 Meg x 64), 2GB (256 Meg x 64)
• Vdd = Vddq = +1.5V ±0.075V
• Vddspd = +3.0V to +3.6V
• Reset pin for improved system stability
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Single rank
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Adjustable data-output drive strength
• Serial presence-detect (SPD) EEPROM
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Figure 1:
240-Pin UDIMM (MO-269 R/C A)
PCB height: 30.0mm (1.181in)
Options
• Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
240-pin DIMM (halogen-free)
• Frequency/CAS latency
–
1.25ns @ CL = 11 (DDR3-1600)
3
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ CL = 8 (DDR3-1066)
2
–
2.5ns @ CL = 5 (DDR3-800)
2
–
2.5ns @ CL = 6 (DDR3-800)
2
1
Marking
None
I
Z
-1G6
-1G4
-1G1
-1G0
-80C
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
3. Not available for 2GB modules.
Table 1:
Key Timing Parameters
Data Rate (MT/s)
CL=11 CL = 10 CL = 9
1600
1333
1333
–
–
–
–
–
1333
–
–
–
–
CL = 8
1066
1066
1066
1066
–
–
CL = 7
–
1066
1066
–
–
–
CL = 6
800
800
800
800
800
800
CL = 5
–
–
–
–
800
–
t
Speed
Industry
Grade Nomenclature
-1G6
-1G4
-1G1
-1G0
-80C
-80B
PC3-12800
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
RCD
(ns)
RP
(ns)
13.75
13.5
13.125
15
12.5
15
t
RC
(ns)
48.75
49.5
50.625
52.5
50
52.5
t
13.75
13.5
13.125
15
12.5
15
PDF: 09005aef837d3ecf/Source: 09005aef837d3e17
JTF8C128_256x64AZ.fm - Rev. A 1/09 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB (x64, SR): 240-Pin DDR3 SDRAM UDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Addressing
1GB
8K
16K A[13:0]
8 BA[2:0]
1Gb (128 Meg x 8)
1K A[9:0]
1 (S0#)
2GB
8K
32K A[14:0]
8 BA[2:0]
2Gb (256 Meg x 8)
1K A[9:0]
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Module
Density
1GB
1GB
1GB
Module
Bandwidth
12.8 GB/s
10.6 GB/s
8.5 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
11-11-11
9-9-9
7-7-7
Part Number
2
Configuration
128 Meg x 64
128 Meg x 64
128 Meg x 64
MT8JTF12864A(I)Z-1G6__
MT8JTF12864A(I)Z-1G4__
MT8JTF12864A(I)Z-1G1__
Table 4:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M8,
1
2Gb DDR3 SDRAM
Module
Density
2GB
2GB
Module
Bandwidth
10.6 GB/s
8.5 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.87ns/1066 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
9-9-9
7-7-7
Part
Number
2
Configuration
256 Meg x 64
256 Meg x 64
MT8JTF25664A(I)Z-1G4__
MT8JTF25664A(I)Z-1G1__
Notes:
1. Data sheets for the base device parts can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT8JTF12864AY-1G1D1.
PDF: 09005aef837d3ecf/Source: 09005aef837d3e17
JTF8C128_256x64AZ.fm - Rev. A 1/09 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR): 240-Pin DDR3 SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
240-Pin DDR3 UDIMM Front
240-Pin DDR3 UDIMM Back
Symbol
Vss
DM5
NC
Vss
DQ46
DQ47
Vss
DQ52
DQ53
Vss
DM6
NC
Vss
DQ54
DQ55
Vss
DQ60
DQ61
Vss
DM7
NC
Vss
DQ62
DQ63
Vss
Vddspd
SA1
SDA
Vss
Vtt
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Vrefdq
Vss
DQ0
DQ1
Vss
DQS0#
DQS0
Vss
DQ2
DQ3
Vss
DQ8
DQ9
Vss
DQS1#
DQS1
Vss
DQ10
DQ11
Vss
DQ16
DQ17
Vss
DQS2#
DQS2
Vss
DQ18
DQ19
Vss
DQ24
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DQ25
Vss
DQS3#
DQS3
Vss
DQ26
DQ27
Vss
NC
NC
Vss
NC
NC
Vss
NC
NC
Vss
NC
NC
CKE0
Vdd
BA2
NC
Vdd
A11
A7
Vdd
A5
A4
Vdd
Notes:
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
A2
Vdd
NU
NU
Vdd
Vdd
Vrefca
NC
Vdd
A10
BA0
Vdd
WE#
CAS#
Vdd
NC
NC
Vdd
NC
Vss
DQ32
DQ33
Vss
DQS4#
DQS4
Vss
DQ34
DQ35
Vss
DQ40
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ41
Vss
DQS5#
DQS5
Vss
DQ42
DQ43
Vss
DQ48
DQ49
Vss
DQS6#
DQS6
Vss
DQ50
DQ51
Vss
DQ56
DQ57
Vss
DQS7#
DQS7
Vss
DQ58
DQ59
Vss
SA0
SCL
SA2
Vtt
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Vss
DQ4
DQ5
Vss
DM0
NC
Vss
DQ6
DQ7
Vss
DQ12
DQ13
Vss
DM1
NC
Vss
DQ14
DQ15
Vss
DQ20
DQ21
Vss
DM2
NC
Vss
DQ22
DQ23
Vss
DQ28
DQ29
151
Vss
152
DM3
153
NC
154
Vss
155 DQ30
156 DQ31
157
Vss
158
NC
159
NC
160
Vss
161
NC
162
NC
163
Vss
164
NC
165
NC
166
Vss
167
NC
168 RESET#
169
NC
170
Vdd
171
NC
172 NC/A14
1
173
Vdd
174
A12
175
A9
176
Vdd
177
A8
178
A6
179
Vdd
180
A3
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
A1
Vdd
Vdd
CK0
CK0#
Vdd
NC
A0
Vdd
BA1
Vdd
RAS#
S0#
Vdd
ODT0
A13
Vdd
NC
Vss
DQ36
DQ37
Vss
DM4
NC
Vss
DQ38
DQ39
Vss
DQ44
DQ45
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
1. Pin 172 is NC for 1GB modules and A14 for 2GB modules.
PDF: 09005aef837d3ecf/Source: 09005aef837d3e17
JTF8C128_256x64AZ.fm - Rev. A 1/09 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR): 240-Pin DDR3 SDRAM UDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A[14:0]
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command to
determine whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or
all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is
also used for BC4/BL8 identification as “BL on-the-fly” during CAS commands. The address
inputs also provide the op-code during the mode register command set
.
A[13:0] address the 1GB
devices; A[14:0] address the 2GB devices.
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register, including MR, EMR,
EMR(2), and EMR(3), is loaded during the LOAD MODE command.
Clock:
CK and CK# are differential clock inputs. All control, command, and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal circuitry
and clocks on the DRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH, along with the input data, during a write access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is designed to match that of the DQ and
DQS pins.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW) termination
resistance internal to the DRAM. When enabled in normal operation, ODT is only applied to the
following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being entered.
Reset:
RESET# is an active LOW CMOS input referenced to Vss. The RESET# input receiver is a
CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 x Vdd and DC LOW
≤
0.2 x Vdd.
Serial address inputs:
These pins are used to configure the SPD EEPROM address range.
Serial clock for presence-detect:
SCL is used to synchronize communication to and from the
SPD EEPROM.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS and DQS# are differential data strobes. Output with read data. Edge-aligned
with read data. Input with write data. Center-aligned with write data. DQS# is only used when
the differential data strobe mode is enabled via the LOAD MODE command.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of the
SPD EEPROM on the module.
Power supply:
1.5V ±0.075V. The component Vdd and Vddq are connected to the module Vdd.
Temperature sensor/SPD EEPROM power supply:
+3.0V to +3.6V.
Reference voltage:
DQ, DM (Vdd/2).
Reference voltage:
Control, command, and address (Vdd/2).
Ground.
Termination voltage:
Used for control, command, and address (Vdd/2).
No connect:
These pins are not connected on the module.
Not used:
These pins are not used in specific module configuration/operations.
BA[2:0]
Input
CK0, CK0#
CKE0
DM[7:0]
Input
Input
Input
ODT0
Input
RAS#, CAS#,
WE#
RESET#
SA[2:0]
SCL
S0#
DQ[63:0]
DQS[7:0],
DQS#[7:0]
SDA
Vdd
Vddspd
Vrefdq
Vrefca
Vss
Vtt
NC
NU
Input
Input
Input
Input
Input
I/O
I/O
I/O
Supply
Supply
Supply
Supply
Supply
Supply
–
–
PDF: 09005aef837d3ecf/Source: 09005aef837d3e17
JTF8C128_256x64AZ.fm - Rev. A 1/09 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR): 240-Pin DDR3 SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
S0#
DQS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1#
DQS1
DM1
Vss
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5#
DQS5
DM5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
Vss
DQS4#
DQS4
DM4
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
CS# DQS DQS#
Functional Block Diagram
U1
U5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2#
DQS2
DM2
Vss
U2
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6#
DQS6
DM6
Vss
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
CS# DQS DQS#
U6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3#
DQS3
DM3
Vss
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
U3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Vss
DQS7#
DQS7
DM7
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U7
DQ
DQ
DQ
DQ
ZQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Vss
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
U4
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
Vss
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U8
DQ
DQ
DQ
DQ
ZQ
BA[2:0]
A[14/13:0]
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
BA[2:0]: DDR3 SDRAM
A[14/13:0]: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
WE#: DDR3 SDRAM
CKE0: DDR3 SDRAM
ODT0: DDR3 SDRAM
RESET#: DDR3 SDRAM
U9
SCL
SPD EEPROM
WP A0
A1
A2
Vss
SA0 SA1 SA2
SDA
CK0
CK0#
DDR3 SDRAM x8
Vddspd
Vdd
Vtt
Vrefca
Vtt
Vrefdq
Vss
SPD EEPROM
DDR3 SDRAM
Control, command, and address termination
DDR3 SDRAM
DDR3 SDRAM
DDR3 SDRAM
Clock, command, control, and address line terminations:
CKE0, A[14/13:0],
RAS#, CAS#, WE#,
S0#, ODT0, BA[2:0]
DDR3
SDRAM
DDR3
SDRAM
CK0
CK0#
Vdd
Notes:
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is
tied to ground. It is used for the calibration of the component’s ODT and output driver.
PDF: 09005aef837d3ecf/Source: 09005aef837d3e17
JTF8C128_256x64AZ.fm - Rev. A 1/09 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
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