Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
T
C
of 0°C to 95°C
– 64ms, 8192 cycle refresh at 0°C to 85°C
– 32ms, 8192 cycle refresh at 85°C to 95°C
Self refresh temperature (SRT)
Write leveling
Multipurpose register
Output driver calibration
Options
1
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm) Rev. H,M,J,K
– 78-ball (9mm x 11.5mm) Rev. D
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) Rev. D
– 96-ball (8mm x 14mm) Rev. K
• Timing – cycle time
– 938ps @ CL = 14 (DDR3-2133)
– 1.071ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C T
C
+95°C)
– Industrial (–40°C T
C
+95°C)
• Revision
Note:
Marking
512M4
256M8
128M16
DA
HX
HA
JT
-093
-107
-125
-15E
-187E
None
IT
:D/:H/:J/:K/
:M
•
•
•
•
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on
http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
-093
1, 2, 3, 4
-107
1, 2, 3
-125
1, 2,
-15E
1,
-187E
Notes:
1.
2.
3.
4.
Data Rate (MT/s)
2133
1866
1600
1333
1066
Target
t
RCD-
t
RP-CL
14-14-14
13-13-13
11-11-11
9-9-9
7-7-7
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.09
13.91
13.75
13.5
13.1
13.09
13.91
13.75
13.5
13.1
13.09
13.91
13.75
13.5
13.1
Backward compatible to 1066, CL = 7 (-187E).
Backward compatible to 1333, CL = 9 (-15E).
Backward compatible to 1600, CL = 11 (-125).
Backward compatible to 1866, CL = 13 (-107).
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Table 2: Addressing
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
Page size
512 Meg x 4
64 Meg x 4 x 8 banks
8K
32K (A[14:0])
8 (BA[2:0])
2K (A[11, 9:0])
1KB
256 Meg x 8
32 Meg x 8 x 8 banks
8K
32K (A[14:0])
8 (BA[2:0])
1K (A[9:0])
1KB
128 Meg x 16
16 Meg x 16 x 8 banks
8K
16K (A[13:0])
8 (BA[2:0])
1K (A[9:0])
2KB
Figure 1: DDR3 Part Numbers
Example Part Number:
MT41J256M8JE-125:M
-
:
Speed
Revision
MT41J
Configuration
Package
Configuration
512 Meg x 4
256 Meg x 8
128 Meg x 16
512M4
256M8
128M16
Temperature
Commercial
Industrial temperature
None
IT
Package
78-ball 9mm x 11.5mm FBGA
78-ball 8mm x 10.5mm FBGA
96-ball 9mm x 14mm FBGA
96-ball 8mm x 14mm FBGA
HX
DA
HA
JT
-093
-107
-125
-15E
-187E
Speed Grade
tCK = 0.938ns, CL = 14
tCK = 1.071ns, CL = 13
tCK = 1.25ns, CL = 11
tCK = 1.5ns, CL = 9
tCK = 1.87ns, CL = 7
Note:
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com
for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
^
:D/:H/:K/:M Revision
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Contents
State Diagram ................................................................................................................................................ 11
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Electrical Specifications – DC and AC .............................................................................................................. 45
DC Operating Conditions ........................................................................................................................... 45
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 70
Slew Rate Definitions for Differential Output Signals .................................................................................... 71
Speed Bin Tables ............................................................................................................................................ 72
Electrical Characteristics and AC Operating Conditions ................................................................................... 77
Command and Address Setup, Hold, and Derating ........................................................................................... 97
Data Setup, Hold, and Derating ...................................................................................................................... 105
Commands – Truth Tables ............................................................................................................................. 114
NO OPERATION ........................................................................................................................................ 117
ZQ CALIBRATION LONG ........................................................................................................................... 117
ZQ CALIBRATION SHORT .......................................................................................................................... 117
Burst Type ................................................................................................................................................. 136
CAS Latency (CL) ....................................................................................................................................... 138
CAS WRITE Latency (CWL) ........................................................................................................................ 143
AUTO SELF REFRESH (ASR) ....................................................................................................................... 144
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 144
SRT versus ASR .......................................................................................................................................... 145
Extended Temperature Usage ........................................................................................................................ 180
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
ODT Off During READs .............................................................................................................................. 202
EtherCAT（Ethernet for Control Automation Technology）是一种基于以太网的开发构架的实时工业现场总线通讯协议，EtherCAT是最快的工业以太网技术之一，同时它提供纳秒级精确同步。相对于设置了相同循环时间的其他总线系统，EtherCAT系统结构通常能减少25%-30%的CPU负载，EtherCAT的出现为系统的实时性能和拓扑的灵活性树立了新的标准。...[详细]
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