48-Lane 12-Port PCIe® Gen2
System Interconnect Switch
®
89HPES48H12G2
Product Brief
The 89HPES48H12G2 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES48H12G2 is a 48-lane, 12-
port system interconnect switch optimized for PCI Express Gen2 packet
switching in high-performance applications, supporting multiple simulta-
neous peer-to-peer traffic flows. Target applications include servers,
storage, communications, embedded systems, and multi-host or intelli-
gent I/O based systems with inter-domain communication.
Utilizing standard PCI Express Gen2 interconnect, the PES48H12G2
provides the most efficient system interconnect switching solution for
applications requiring high throughput, low latency, and simple board
layout with a minimum number of board layers. Each lane is capable of 5
GT/s of bandwidth in both directions and is fully compliant with PCI
Express Base specification 2.0.
Device Overview
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Crosslink support
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Automatic lane reversal
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Autonomous and software managed link width and speed
control
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Per lane SerDes configuration
• De-emphasis
• Receive equalization
• Drive strength
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Switch Partitioning
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IDT proprietary feature that creates logically independent
switches in the device
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Supports up to 12 fully independent switch partitions
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Configurable downstream port device numbering
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Supports dynamic reconfiguration of switch partitions
• Dynamic port reconfiguration — downstream, upstream
• Dynamic migration of ports between partitions
• Movable upstream port within and between switch partitions
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Initialization / Configuration
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Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
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Common switch configurations are supported with pin strap-
ping (no external components)
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Supports in-system Serial EEPROM initialization/program-
ming
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Quality of Service (QoS)
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Port arbitration
• Round robin
• Weighted Round Robin (WRR)
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Request metering
• IDT proprietary feature that balances bandwidth among
switch ports for maximum system throughput
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High performance switch core architecture
• Combined Input Output Queued (CIOQ) switch architecture
with large buffers
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Multicast
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Compliant to the PCI-SIG multicast ECN
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Supports arbitrary multicasting of Posted transactions
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Supports 64 multicast groups
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Multicast overlay mechanism support
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ECRC regeneration support
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Clocking
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Supports 100 MHz and 125 MHz reference clock frequencies
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Flexible clocking modes
• Common clock
• Non-common clock
Features
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High Performance Non-Blocking Switch Architecture
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48-lane 12-port PCIe switch
• Six x8 ports switch ports each of which can bifurcate to two
x4 ports (total of twelve x4 ports)
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Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Gen1 operation
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Delivers up to
48 GBps (384 Gbps)
of switching capacity
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Supports 128 Bytes to 2 KB maximum payload size
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Low latency cut-through architecture
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Supports one virtual channel and eight traffic classes
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Standards and Compatibility
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PCI Express Base Specification 2.0 compliant
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Implements the following optional PCI Express features
• Advanced Error Reporting (AER) on all ports
• End-to-End CRC (ECRC)
• Access Control Services (ACS)
• Power Budgeting Enhanced Capability
• Device Serial Number Enhanced Capability
• Sub-System ID and Sub-System Vendor ID Capability
• Internal Error Reporting ECN
• Multicast ECN
• VGA and ISA enable
• L0s and L1 ASPM
• ARI ECN
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Port Configurability
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x4 and x8 ports
• Ability to merge adjacent x4 ports to create a x8 port
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Automatic per port link width negotiation
(x8 --> x4 --> x2 --> x1)
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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©
2008 Integrated Device Technology, Inc.
September 25, 2008
IDT 89HPES48H12G2 Product Brief
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• Local port clock with SSC and port reference clock input
Hot-Plug and Hot Swap
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Hot-plug controller on all ports
• Hot-plug supported on all downstream switch ports
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All ports support hot-plug using low-cost external I
2
C I/O
expanders
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Configurable presence detect supports card and cable appli-
cations
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GPE output pin for hot-plug event notification
• Enables SCI/SMI generation for legacy operating system
support
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Hot swap capable I/O
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Power Management
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Supports D0, D3hot and D3 power management states
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Active State Power Management (ASPM)
• Supports L0, L0s, L1, L2/L3 Ready and L3 link states
• Configurable L0s and L1 entry timers allow performance/
power-savings tuning
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Supports PCI Express Power Budgeting Capability
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SerDes power savings
• Supports low swing / half-swing SerDes operation
• SerDes optionally turned-off in D3hot
• SerDes associated with unused ports are turned-off
• SerDes associated with unused lanes are placed in a low
power state
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9 General Purpose I/O
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Reliability, Availability and Serviceability (RAS)
ECRC support
AER on all ports
SECDED ECC protection on all internal RAMs
End-to-end data path parity protection
Checksum Serial EEPROM content protected
Autonomous link reliability (preserves system operation in the
presence of faulty links)
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Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
◆
Test and Debug
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On-chip link activity and status outputs available for Port 0
(upstream port)
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Per port link activity and status outputs available using
external I
2
C I/O expander for all other ports
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SerDes test modes
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Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
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Power Supplies
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Requires only two power supply voltages (1.0 V and 2.5 V)
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No power sequencing requirements
◆
Packaged in a 27mm x 27mm 676-ball Flip Chip BGA with
1mm ball spacing
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September 25, 2008
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