NLHV4051, NLHV4052,
NLHV4053
Analog
Multiplexers/Demultiplexers
The NLHV4051, NLHV4052, and NLHV4053 analog multiplexers
are digitally−controlled analog switches. The NLHV4051 effectively
implements an SP8T solid state switch, the NLHV4052 a DP4T, and
the NLHV4053 a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
Features
1
SOIC−16
D SUFFIX
CASE 751B
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1
TSSOP−16
DT SUFFIX
CASE 948F
•
•
•
•
•
•
•
•
•
•
Triple Diode Protection on Control Inputs
Switch Function is Break Before Make
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Analog Voltage Range (V
DD
− V
EE
) = 3.0 to 18 V
Note: V
EE
must be
≤
V
SS
Linearized Transfer Characteristics
Low−noise − 12 nV/√Cycle, f
≥
1.0 kHz Typical
Pin−for−Pin Replacement for CD4051, CD4052, and CD4053
For 4PDT Switch, See MC14551B
For Lower R
ON
, Use the HC4051, HC4052, or HC4053 High−Speed
CMOS Devices
These Devices are Pb−Free and are RoHS Compliant
MARKING DIAGRAMS
16
NLHVG
405x
AWLYWW
1
SOIC−16
16
NLHV
405x
ALYWG
G
1
TSSOP−16
x
A
WL, L
Y
WW, W
G or
G
= 1, 2, or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
,
V
out
I
in
I
SW
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
(Referenced to V
EE
, V
SS
≥
V
EE
)
Input or Output Voltage Range
(DC or Transient) (Referenced to V
SS
for
Control Inputs and V
EE
for Switch I/O)
Input Current (DC or Transient)
per Control Pin
Switch Through Current
Power Dissipation per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
Unit
V
V
+10
±25
500
−55 to +125
−65 to +150
260
mA
mA
mW
°C
°C
°C
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained to
the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
V
SS
, V
EE
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2016
1
April, 2017 − Rev. 0
Publication Order Number:
NLHV4051/D
NLHV4051, NLHV4052, NLHV4053
NLHV4051
8−Channel Analog
Multiplexer/Demultiplexer
6
11
10
9
13
14
15
12
1
5
2
4
INHIBIT
A
B
C
X0
X1
X
3
X2
COMMON
X3
OUT/IN
X4
X5
X6
X7
V
DD
= PIN 16
V
SS
= PIN 8
V
EE
= PIN 7
NLHV4052
Dual 4−Channel Analog
Multiplexer/Demultiplexer
6
10
9
12
14
15
11
1
5
2
4
INHIBIT
A
X
B
X0
X1
X2
X3
Y0
Y
Y1
Y2
Y3
NLHV4053
Triple 2−Channel Analog
Multiplexer/Demultiplexer
6
11
10
9
12
13
2
1
5
3
INHIBIT
X
A
B
C
X0
Y
X1
Y0
Y1
Z
Z0
Z1
14
CONTROLS
CONTROLS
13
COMMONS
OUT/IN
3
CONTROLS
15
COMMONS
OUT/IN
SWITCHES
IN/OUT
SWITCHES
IN/OUT
SWITCHES
IN/OUT
4
V
DD
= PIN 16
V
SS
= PIN 8
V
EE
= PIN 7
V
DD
= PIN 16
V
SS
= PIN 8
V
EE
= PIN 7
Note: Control Inputs referenced to V
SS
, Analog Inputs and Outputs reference to V
EE
. V
EE
must be
≤
V
SS
.
PIN ASSIGNMENT
NLHV4051
X4
X6
X
X7
X5
INH
V
EE
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
X2
X1
X0
X3
A
B
C
Y0
Y2
Y
Y3
Y1
INH
V
EE
V
SS
NLHV4052
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
X2
X1
X
X0
X3
A
B
Y1
Y0
Z1
Z
Z0
INH
V
EE
V
SS
NLHV4053
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Y
X
X1
X0
A
B
C
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NLHV4051, NLHV4052, NLHV4053
ELECTRICAL CHARACTERISTICS
−55_C
Characteristic
Symbol
V
DD
−
5.0
10
15
Test Conditions
V
DD
– 3.0
≥
V
SS
≥
V
EE
Control Inputs:
V
in
= V
SS
or V
DD
,
Switch I/O: V
EE
v
V
I/O
v
V
DD
, and
DV
switch
v
500 mV (Note 3)
T
A
= 25_C only (The
channel component,
(V
in
– V
out
)/R
on
, is
not included.)
Min
Max
Min
25_C
Typ
(Note 2)
Max
125_C
Min
Max
Unit
SUPPLY REQUIREMENTS
(Voltages Referenced to V
EE
)
Power Supply Voltage
Range
Quiescent Current Per
Package
V
DD
I
DD
3.0
−
−
−
18
5.0
10
20
3.0
−
−
−
−
0.005
0.010
0.015
18
5.0
10
20
3.0
−
−
−
18
150
300
600
V
mA
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
I
D(AV)
5.0
10
15
Typical
(0.07
mA/kHz)
f + I
DD
(0.20
mA/kHz)
f + I
DD
(0.36
mA/kHz)
f + I
DD
mA
CONTROL INPUTS — INHIBIT, A, B, C
(Voltages Referenced to V
SS
)
Low−Level Input Voltage
V
IL
5.0
10
15
5.0
10
15
15
−
R
on
= per spec,
I
off
= per spec
R
on
= per spec,
I
off
= per spec
V
in
= 0 or V
DD
−
−
−
3.5
7.0
11
−
−
1.5
3.0
4.0
−
−
−
±0.1
−
−
−
−
3.5
7.0
11
−
−
2.25
4.50
6.75
2.75
5.50
8.25
±0.00001
5.0
1.5
3.0
4.0
−
−
−
±0.1
7.5
−
−
−
3.5
7.0
11
−
−
1.5
3.0
4.0
−
−
−
1.0
−
V
High−Level Input Voltage
V
IH
V
Input Leakage Current
Input Capacitance
I
in
C
in
V
I/O
mA
pF
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z
(Voltages Referenced to V
EE
)
Recommended
Peak−to−Peak Voltage
Into or Out of the Switch
Recommended Static or
Dynamic Voltage Across
the Switch (Note 3)
(Figure 5)
Output Offset Voltage
ON Resistance
−
Channel On or Off
0
V
DD
0
−
V
DD
0
V
DD
V
PP
DV
switch
−
Channel On
0
600
0
−
600
0
300
mV
V
OO
R
on
−
5.0
10
15
5.0
10
15
15
V
in
= 0 V, No Load
DV
switch
v
500 mV
(Note 3) V
in
= V
IL
or V
IH
(Control), and V
in
=
0 to V
DD
(Switch)
−
−
−
−
−
−
−
−
800
400
220
70
50
45
±100
−
−
−
−
−
−
−
−
10
250
120
80
25
10
10
±0.05
−
1050
500
280
70
50
45
±100
−
−
−
−
−
−
−
−
−
1200
520
300
135
95
65
±1000
mV
W
DON
Resistance Between
Any Two Channels in the
Same Package
Off−Channel Leakage
Current (Figure 10)
DR
on
W
I
off
V
in
= V
IL
or V
IH
(Control) Channel to
Channel or Any One
Channel
Inhibit = V
DD
Inhibit = V
DD
(NLHV4051)
(NLHV4052)
(NLHV4053)
Pins Not Adjacent
Pins Adjacent
−
nA
Capacitance, Switch I/O
Capacitance, Common O/I
C
I/O
C
O/I
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10
60
32
17
0.15
0.47
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
pF
pF
Capacitance, Feedthrough
(Channel Off)
C
I/O
−
−
pF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
3. For voltage drops across the switch (DV
switch
) > 600 mV (> 300 mV at high temperature), excessive V
DD
current may be drawn, i.e. the
current out of the switch may contain both V
DD
and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.)
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3
NLHV4051, NLHV4052, NLHV4053
ELECTRICAL CHARACTERISTICS
(Note 4) (C
L
= 50 pF, T
A
= 25_C) (V
EE
v
V
SS
unless otherwise indicated)
Characteristic
Propagation Delay Times (Figure 6)
Switch Input to Switch Output (R
L
= 1 kW)
NLHV4051
t
PLH
, t
PHL
= (0.17 ns/pF) C
L
+ 26.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) C
L
+ 11 ns
t
PLH
, t
PHL
= (0.06 ns/pF) C
L
+ 9.0 ns
NLHV4052
t
PLH
, t
PHL
= (0.17 ns/pF) C
L
+ 21.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) C
L
+ 8.0 ns
t
PLH
, t
PHL
= (0.06 ns/pF) C
L
+ 7.0 ns
NLHV4053
t
PLH
, t
PHL
= (0.17 ns/pF) C
L
+ 16.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) C
L
+ 4.0 ns
t
PLH
, t
PHL
= (0.06 ns/pF) C
L
+ 3.0 ns
Inhibit to Output (R
L
= 10 kW, V
EE
= V
SS
)
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
NLHV4051
t
PHZ
, t
PLZ
,
t
PZH
, t
PZL
5.0
10
15
5.0
10
15
5.0
10
15
t
PLH
, t
PHL
5.0
10
15
5.0
10
15
5.0
10
15
−
BW
10
10
360
160
120
325
130
90
300
120
80
0.07
17
720
320
240
650
260
180
600
240
160
−
−
ns
350
170
140
300
155
125
275
140
110
700
340
280
600
310
250
550
280
220
ns
Symbol
t
PLH
, t
PHL
V
DD
– V
EE
Vdc
Typ
(Note 5)
All Types
Max
Unit
ns
5.0
10
15
5.0
10
15
5.0
10
15
35
15
12
30
12
10
25
8.0
6.0
90
40
30
ns
75
30
25
ns
65
20
15
ns
NLHV4052
NLHV4053
ns
Control Input to Output (R
L
= 1 kW, V
EE
= V
SS
)
NLHV4051
ns
NLHV4052
NLHV4053
ns
Second Harmonic Distortion
(R
L
= 10KW, f = 1 kHz) V
in
= 5 V
PP
Bandwidth (Figure 7)
(R
L
= 50
W,
V
in
= 1/2 (V
DD
−V
EE
) p−p, C
L
= 50pF
20 Log (V
out
/V
in
) = − 3 dB)
Off Channel Feedthrough Attenuation (Figure 7)
R
L
= 1KW, V
in
= 1/2 (V
DD
− V
EE
) p−p
f
in
= 4.5 MHz — NLHV4051
f
in
= 30 MHz — NLHV4052
f
in
= 55 MHz — NLHV4053
Channel Separation (Figure 8)
(R
L
= 1 kW, V
in
= 1/2 (V
DD
−V
EE
) p−p,
f
in
= 3.0 MHz
Crosstalk, Control Input to Common O/I (Figure 9)
(R
1
= 1 kW, R
L
= 10 kW
Control t
TLH
= t
THL
= 20 ns, Inhibit = V
SS
)
%
MHz
−
10
–50
−
dB
−
10
–50
−
dB
−
10
75
−
mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The formulas given are for the typical characteristics only at 25_C.
5. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
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NLHV4051, NLHV4052, NLHV4053
V
DD
IN/OUT
V
DD
V
DD
OUT/IN
V
EE
V
DD
LEVEL
CONVERTED
CONTROL
IN/OUT
OUT/IN
V
EE
CONTROL
Figure 1. Switch Circuit Schematic
TRUTH TABLE
Control Inputs
Select
Inhibit
0
0
0
0
0
0
0
0
C*
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
NLHV4051
X0
X1
X2
X3
X4
X5
X6
X7
None
ON Switches
NLHV4052
Y0
Y1
Y2
Y3
X0
X1
X2
X3
NLHV4053
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
None
X0
X1
X0
X1
X0
X1
X0
X1
INH
A
B
C
6
11
10
9
8
X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4
16
V
DD
BINARY TO 1-OF-8
DECODER WITH
INHIBIT
V
EE
LEVEL
CONVERTER
V
SS
7
3 X
1
x
x x
None
*Not applicable for MC14052
x = Don’t Care
Figure 2. NLHV4051 Functional Diagram
16
INH 6
A 10
B 9
8
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
V
SS
7
V
EE
13 X
V
DD
16
V
DD
BINARY TO 1-OF-2
DECODER WITH
INHIBIT
V
EE
14 X
LEVEL
CONVERTER
BINARY TO 1-OF-4
DECODER WITH
INHIBIT
INH
A
B
C
6
11
10
9
8
LEVEL
CONVERTER
V
SS
7
X0 12
X1 13
Y0 2
3 Y
Y1 1
Z0 5
Z1 3
15 Y
4 Z
Figure 3. NLHV4052 Functional Diagram
Figure 4. NLHV4053 Functional Diagram
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