HIGH-SPEED 3.3V 512K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
.eatures:
x
PRELIMINARY
IDT70V7339S
x
x
x
x
x
x
512K x 18 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
–
64 independent 8K x 18 banks
– 9 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
x
x
x
x
x
x
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 144-pin Thin Quad Flatpack (TQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
144-pin TQFP package.
.unctional Block Diagram
PL/FT
L
OPT
L
CLK
L
ADS
L
CNTEN
L
REPEAT
L
R/W
L
CE
0L
CE
1L
UB
L
LB
L
OE
L
PL/FT
R
OPT
R
CLK
R
ADS
R
CNTEN
R
REPEAT
R
R/W
R
CE
0R
CE
1R
UB
R
LB
R
OE
R
CONTROL
LOGIC
MUX
8Kx18
MEMORY
ARRAY
(BANK 0)
MUX
CONTROL
LOGIC
I/O
0L-17L
I/O
CONTROL
MUX
8Kx18
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O
0R-17R
A
12L
A
0L
BA
5L
BA
4L
BA
3L
BA
2L
BA
1L
BA
0L
ADDRESS
DECODE
ADDRESS
DECODE
A
12R
A
0R
BA
5R
BA
4R
BA
3R
BA
2R
BA
1R
BA
0R
BANK
DECODE
MUX
8Kx18
MEMORY
ARRAY
(BANK 63)
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
MUX
,
TDI
TDO
JTAG
TMS
TCK
TRST
5628 drw 01
NOVEMBER 2001
1
DSC 5628/4
©2001 Integrated Device Technology, Inc.
IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Description:
The IDT70V7339 is a high-speed 512Kx18 (9Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
8Kx18 banks. The device has two independent ports with separate
control, address, and I/O pins for each port, allowing each port to access
any 8Kx18 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
address pins under the user's direct control.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data
register, the IDT70V7339 has been optimized for applications having
unidirectional or bidirectional data flow in bursts. An automatic power down
feature, controlled by CE
0
and CE
1
, permits the on-chip circuitry of each
port to enter a very low standby power mode. The dual chip enables also
facilitate depth expansion.
The 70V7339 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device(V
DD
) remains at 3.3V. Please refer also to the
functional description on page 19.
Pin Configuration
(1,2,3,4)
1 1 /2 0 /0 1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
IO
9L
B1
NC
B2
V
SS
B3
TDO
B4
NC
B5
BA
3L
B6
A
12L
B7
A
8L
B8
NC
B9
V
DD
B10
CLK
L
CNTEN
L
A
4L
B11
B12
B13
A
0L
B14
OPT
L
B15
NC
B16
V
SS
B17
NC
C1
V
SS
C2
NC
C3
TDI
C4
BA
4L
C5
BA
0L
C6
A
9L
C7
NC
C8
CE
0L
C9
V
SS
C10
ADS
L
C11
A
5L
C12
A
1L
C13
V
SS
V
DDQR
I/O
8L
C14
C15
C16
NC
C17
V
DDQL
I/O
9R
V
DDQR
PL/
FT
L
BA
5L
BA
1L
D1
D2
D3
D4
D5
D6
A
10L
D7
UB
L
D8
CE
1L
D9
V
SS
D10
R/W
L
D11
A
6L
D12
A
2L
D13
V
DD
D14
I/O
8R
D15
NC
D16
V
SS
D17
NC
E1
V
SS
E2
I/O
10L
E3
NC
E4
BA
2L
A
11L
A
7L
LB
L
V
DD
OE
L
REPEAT
L
A
3L
V
DD
NC
E14
V
DDQL
I/O
7L
E15
E16
I/O
7R
E17
I/O
11L
F1
NC
F2
V
DDQR
I/O
10R
F3
F4
I/O
6L
F14
NC
F15
V
SS
F16
NC
F17
V
DDQL
I/O
11R
G1
G2
NC
G3
V
SS
G4
V
SS
G14
I/O
6R
G15
NC
G16
V
DDQR
G17
NC
H1
V
SS
H2
I/O
12L
H3
NC
H4
NC
V
DDQL
I/O
5L
H15
H16
NC
H17
V
DD
J1
NC
J2
V
DDQR
I/O
12R
J3
J4
70V7339BF
BF-208
(5)
208-Pin fpBGA
Top View
(6)
H14
V
DD
J14
NC
J15
V
SS
J16
I/O
5R
J17
V
DDQL
V
DD
K1
K2
V
SS
K3
V
SS
K4
V
SS
K14
V
DD
K15
V
SS
V
DDQR
K16
K17
I/O
14R
L1
V
SS
L2
I/O
13R
V
SS
L3
L4
I/O
3R
V
DDQL
I/O
4R
L14
L15
L16
V
SS
L17
NC
M1
I/O
14L
V
DDQR
I/O
13L
M2
M3
M4
NC
M14
I/O
3L
M15
V
SS
M16
I/O
4L
M17
V
DDQL
N1
NC
N2
I/O
15R
V
SS
N3
N4
V
SS
N14
NC
N15
I/O
2R
V
DDQR
N16
N17
NC
P1
V
SS
P2
NC
P3
I/O
15L
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
I/O
1R
V
DDQL
P14
P15
NC
P16
I/O
2L
P17
I/O
16R
I/O
16L
V
DDQR
R1
R2
R3
NC
R4
TRST
BA
3R
A
12R
R5
R6
R7
A
8R
R8
NC
R9
V
DD
R10
CLK
R
CNTEN
R
A
4R
R11
R12
R13
NC
R14
I/O
1L
R15
V
SS
R16
NC
R17
V
SS
T1
NC
T2
I/O
17R
TCK
T3
T4
BA
4R
BA
0R
T5
T6
A
9R
T7
NC
T8
CE
0R
T9
V
SS
T10
ADS
R
T11
A
5R
T12
A
1R
T13
V
SS
T14
V
DDQL
I/O
0R
V
DDQR
T15
T16
T17
NC
U1
I/O
17L
V
DDQL
TMS
U2
U3
U4
BA
5R
BA
1R
U5
U6
A
10R
U7
UB
R
U8
CE
1R
U9
V
SS
U10
R/W
R
A
6R
U12
A
2R
U13
V
SS
U14
NC
U15
V
SS
U16
NC
U17
V
SS
NC
PL/
FT
R
NC
BA
2R
A
11R
A
7R
LB
R
V
DD
OE
R
A
3R
A
0R
V
DD
OPT
R
NC
I/O
0L
,
5628 drw 02c
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4)
(con't.)
70V7339BC
BC-256
(5)
256-Pin BGA
Top View
(6)
11/20/01
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
B1
TDI
B2
NC
B3
BA
4L
B4
BA1
L
B5
A
11L
B6
A
8L
B7
NC
B8
CE
1L
B9
OE
L
B10
CNTEN
L
B11
A
5L
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
NC
C1
NC
C2
TDO
C3
BA
5L
C4
BA
2L
C5
A
12L
C6
A
9L
C7
UB
L
C8
CE
0L
R/W
L
REPEAT
L
C9
C10
C11
A
4L
C12
A
1L
C13
V
DD
C14
NC
C15
NC
C16
NC
D1
I/O
9L
D2
V
SS
D3
BA
3L
D4
BA
0L
D5
A
10L
D6
A
7L
D7
NC
D8
LB
L
D9
CLK
L
ADS
L
D10
D11
A
6L
D12
A
3L
D13
OPT
L
D14
NC
D15
I/O
8L
D16
NC
E1
I/O
9R
E2
NC
E3
PL/FT
L
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
NC
E14
NC
E15
I/O
8R
E16
I/O
10R
I/O
10L
F1
F2
NC
F3
V
DDQL
F4
V
DD
F5
V
DD
F6
V
SS
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
F12
F13
NC
F14
I/O
7L
F15
I/O
7R
F16
I/O
11L
G1
NC
G2
I/O
11R
V
DDQL
G3
G4
V
DD
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
V
DDQR
I/O
6R
G12
G13
G14
NC
G15
I/O
6L
G16
NC
H1
NC
H2
I/O
12L
V
DDQR
H3
H4
V
SS
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
I/O
5L
H13
H14
NC
H15
NC
H16
NC
J1
I/O
12R
J2
NC
J3
V
DDQR
V
SS
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
J13
NC
J14
NC
J15
I/O
5R
J16
I/O
13L
I/O
14R
I/O
13R
V
DDQL
K1
K2
K3
K4
V
SS
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
DDQR
I/O
4R
I/O
3R
K13
K14
K15
I/O
4L
K16
NC
L1
NC
L2
I/O
14L
V
DDQL
L3
L4
V
SS
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
L13
NC
L14
NC
L15
I/O
3L
L16
I/O
15L
M1
NC
M2
I/O
15R
V
DDQR
M3
M4
V
DD
M5
V
SS
M6
V
SS
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
2L
M13
M14
NC
M15
I/O
2R
M16
I/O
16R
I/O
16L
N1
N2
NC
N3
V
DDQR
N4
V
DD
N5
V
DD
N6
V
SS
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
N12
V
DDQL
I/O
1R
N13
N14
I/O
1L
N15
NC
N16
NC
P1
I/O
17R
P2
NC
P3
PL/FT
R
V
DDQR
V
DDQR
V
DDQL
P4
P5
P6
P7
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P8
P9
P10
P11
P12
V
DD
P13
NC
P14
I/O
0R
P15
NC
P16
NC
R1
I/O
17L
TMS
R2
R3
BA
3R
BA
0R
R4
R5
A
10R
R6
A
7R
R7
NC
R8
LB
R
R9
CLK
R
ADS
R
R10
R11
A
6R
R12
A
3R
R13
NC
R14
NC
R15
I/O
0L
R16
NC
T1
NC
T2
TRST
BA
5R
T3
T4
BA
2R
T5
A
12R
T6
A
9R
T7
UB
R
T8
CE
0R
T9
R/W
R
REPEAT
R
T10
T11
A
4R
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
,
NC
TCK
NC
BA
4R
BA
1R
A
11R
A
8R
NC
CE
1R
OE
R
CNTEN
R
A
5R
A
2R
A
0R
NC
NC
5628 drw 02d
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
,
6.42
3
IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
11/20/01
V
SS
V
DDQR
V
SS
I/O
9L
I/O
9R
I/O
10L
I/O
10R
I/O
11L
I/O
11R
V
DDQL
V
SS
I/O
12L
I/O
12R
V
DDQR
V
SS
V
DD
V
DD
V
SS
V
SS
V
DDQL
V
SS
I/O
13R
I/O
13L
I/O
14R
I/O
14L
V
DDQR
V
SS
I/O
15R
I/O
15L
I/O
16R
I/O
16L
I/O
17R
I/O
17L
V
SS
V
DDQL
NC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PL/FT
L
NC
NC
BA
5L
BA
4L
BA
3L
BA
2L
BA
1L
BA
0L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
UB
L
LB
L
CE
1L
CE
0L
V
DD
V
SS
CLK
L
OE
L
R/W
L
ADS
L
CNTEN
L
REPEAT
L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
V
DD
V
SS
Pin Configuration
(1,2,3,4,7)
(con't.)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
70V7339DD
DD-144
(5)
144-Pin TQFP
Top View
(6)
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
OPT
L
V
DDQR
V
SS
I/O
8L
I/O
8R
I/O
7L
I/O
7R
I/O
6L
I/O
6R
V
SS
V
DDQL
I/O
5L
I/O
5R
V
SS
V
DDQR
V
DD
V
DD
V
SS
V
SS
V
SS
V
DDQL
I/O
4R
I/O
4L
I/O
3R
I/O
3L
V
SS
V
DDQR
I/O
2R
I/O
2L
I/O
1R
I/O
1L
I/O
0R
I/O
0L
V
SS
V
DDQL
OPT
R
PL/FTR
NC
NC
BA
5R
BA
4R
BA
3R
BA
2R
BA
1R
BA
0R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
UB
R
LB
R
CE
1R
CE
0R
V
DD
V
SS
CLK
R
OE
R
R/W
R
ADS
R
CNTEN
R
REPEAT
R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
V
DD
V
SS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
5628 drw 02a
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 20mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. Due to the limited pin count, JTAG is not supported in the DD-144 package.
6.42
4
IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
BA
0L
- BA
5L
A
0L
- A
12L
I/O
0L
- I/O
17L
CLK
L
PL/FT
L
ADS
L
CNTEN
L
REPEAT
L
LB
L
,
UB
L
V
DDQL
OPT
L
V
DD
V
SS
TDI
TDO
TCK
TMS
TRST
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
BA
0R
- BA
5R
A
0R
- A
12R
I/O
0R
- I/O
17R
CLK
R
PL/FT
R
ADS
R
CNTEN
R
REPEAT
R
LB
R
,
UB
R
V
DDQR
OPT
R
Chip Enables
Read/Write Enable
Output Enable
Bank Address
(4)
Address
Data Input/Output
Clock
Pipeline/Flow-Through
Address Strobe Enable
Counter Enable
Counter Repeat
(3)
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)
(1)
Option for selecting V
DDQX
(1,2)
Power (3.3V)
(1)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5628 tbl 01
Names
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX
must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
4. Accesses by the ports into specific banks are controlled by the bank address
pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA
0L
- BA
5L
≠
BA
0R
- BA
5R
). In the event that both ports try to access the
same bank at the same time, neither access will be valid, and data at the two
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).
6.42
5
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