STP20NK50Z - STW20NK50Z
N-CHANNEL 500V - 0.23Ω - 20A TO-220/TO-247
Zener-Protected SuperMESH™Power MOSFET
TARGET DATA
TYPE
STP20NK50Z
STW20NK50Z
s
s
s
s
s
s
V
DSS
500 V
500 V
R
DS(on)
< 0.27
Ω
< 0.27
Ω
I
D
20 A
20 A
Pw
190 W
190 W
TYPICAL R
DS
(on) = 0.23
Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
GATE CHARGE MINIMIZED
VERY LOW INTRINSIC CAPACITANCES
VERY GOOD MANUFACTURING
REPEATIBILITY
3
2
1
TO-220
TO-247
DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established strip-
based PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is tak-
en to ensure a very good dv/dt capability for the
most demanding applications. Such series comple-
ments ST full range of high voltage MOSFETs in-
cluding revolutionary MDmesh™ products.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
HIGH CURRENT, HIGH SPEED SWITCHING
s
IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
s
ORDERING INFORMATION
SALES TYPE
STP20NK50Z
STW20NK50Z
MARKING
P20NK50Z
W20NK50Z
PACKAGE
TO-220
TO-247
PACKAGING
TUBE
TUBE
July 2003
1/7
STP20NK50Z - STW20NK50Z
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
( )
P
TOT
V
ESD(G-S)
dv/dt (1)
T
j
T
stg
Parameter
STP20NK50Z
Value
STW20NK50Z
Unit
V
V
V
20
10
64
190
1.51
A
A
A
W
W/°C
V
V/ns
°C
°C
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 kΩ)
Gate- source Voltage
Drain Current (continuos) at T
C
= 25°C
Drain Current (continuos) at T
C
= 100°C
Drain Current (pulsed)
Total Dissipation at T
C
= 25°C
Derating Factor
Gate source ESD(HBM-C=100pF, R=1.5KΩ)
Peak Diode Recovery voltage slope
Operating Junction Temperature
Storage Temperature
20
10
64
190
1.51
500
500
± 30
4000
4.5
-55 to 150
-55 to 150
( ) Pulse width limited by safe operating area
(1) I
SD
≤20A,
di/dt
≤200A/µs,
V
DD
≤
V
(BR)DSS
, T
j
≤
T
JMAX.
(*) Limited only by maximum temperature allowed
THERMAL DATA
TO-220
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case Max
Thermal Resistance Junction-ambient Max
Maximum Lead Temperature For Soldering Purpose
0.66
62.5
300
TO-247
0.66
50
°C/W
°C/W
°C
AVALANCHE CHARACTERISTICS
Symbol
I
AR
E
AS
Parameter
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
Single Pulse Avalanche Energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Max Value
20
TBD
Unit
A
mJ
GATE-SOURCE ZENER DIODE
Symbol
BV
GSO
Parameter
Gate-Source Breakdown
Voltage
Test Conditions
Igs=± 1mA (Open Drain)
Min.
30
Typ.
Max.
Unit
V
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.
2/7
STP20NK50Z - STW20NK50Z
ELECTRICAL CHARACTERISTICS
(TCASE =25°C UNLESS OTHERWISE SPECIFIED)
ON/OFF
Symbol
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
Parameter
Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
Gate Threshold Voltage
Static Drain-source On
Resistance
Test Conditions
I
D
= 1 mA, V
GS
= 0
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 °C
V
GS
= ± 20V
V
DS
= V
GS
, I
D
= 250µA
V
GS
= 10V, I
D
= 10 A
3
3.75
0.23
Min.
500
1
50
±10
4.5
0.27
Typ.
Max.
Unit
V
µA
µA
µA
V
Ω
DYNAMIC
Symbol
g
fs
(1)
C
iss
C
oss
C
rss
C
oss eq.
(3)
Parameter
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Equivalent Output
Capacitance
Parameter
Turn-on Delay Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
V
DS
= 8 V
,
I
D
= 10 A
V
DS
= 25V, f = 1 MHz, V
GS
= 0
Min.
Typ.
TBD
2600
400
55
TBD
Max.
Unit
S
pF
pF
pF
pF
V
GS
= 0V, V
DS
= 0V to 400V
SWITCHING ON
Symbol
t
d(on)
t
r
Q
g
Q
gs
Q
gd
Test Conditions
V
DD
= 250 V, I
D
= 10 A
R
G
= 4.7Ω V
GS
= 10 V
(Resistive Load see, Figure 3)
V
DD
= 400V, I
D
= 20 A,
V
GS
= 10V
Min.
Typ.
TBD
TBD
95
TBD
TBD
Max.
Unit
ns
ns
nC
nC
nC
SWITCHING OFF
Symbol
t
d(off)
t
f
t
r(Voff)
t
f
t
c
Parameter
Turn-off Delay Time
Fall Time
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
V
DD
= 250 V, I
D
= 10 A
R
G
= 4.7Ω V
GS
= 10 V
(Resistive Load see, Figure 3)
V
DD
= 400V, I
D
= 20 A,
R
G
= 4.7Ω, V
GS
= 10V
(Inductive Load see, Figure 5)
Min.
Typ.
TBD
TBD
TBD
TBD
TBD
Max.
Unit
ns
ns
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
I
SD
I
SDM
(2)
V
SD
(1)
t
rr
Q
rr
I
RRM
Parameter
Source-drain Current
Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 20 A, V
GS
= 0
I
SD
= 20 A, di/dt = 100A/µs
V
DD
= 35V, T
j
= 150°C
(see test circuit, Figure 5)
TBD
TBD
TBD
Test Conditions
Min.
Typ.
Max.
TBD
TBD
TBD
Unit
A
A
V
ns
µC
A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80%
V
DSS
.
3/7
STP20NK50Z - STW20NK50Z
Fig. 1:
Unclamped Inductive Load Test Circuit
Fig. 2:
Unclamped Inductive Waveform
Fig. 3:
Switching Times Test Circuit For
Resistive Load
Fig. 4:
Gate Charge test Circuit
Fig. 5:
Test Circuit For Inductive Load Switching
And Diode Recovery Times
4/7
STP20NK50Z - STW20NK50Z
TO-220 MECHANICAL DATA
DIM.
MIN.
A
C
D
D1
E
F
F1
F2
G
G1
H2
L2
L4
L5
L6
L7
L9
DIA.
13.0
2.65
15.25
6.2
3.5
3.75
0.49
0.61
1.14
1.14
4.95
2.4
10.0
16.4
14.0
2.95
15.75
6.6
3.93
3.85
0.511
0.104
0.600
0.244
0.137
0.147
4.40
1.23
2.40
1.27
0.70
0.88
1.70
1.70
5.15
2.7
10.40
0.019
0.024
0.044
0.044
0.194
0.094
0.393
0.645
0.551
0.116
0.620
0.260
0.154
0.151
mm
TYP.
MAX.
4.60
1.32
2.72
MIN.
0.173
0.048
0.094
0.050
0.027
0.034
0.067
0.067
0.203
0.106
0.409
inch
TYP.
MAX.
0.181
0.051
0.107
A
C
D1
L2
D
F1
G1
E
Dia.
L5
L7
L6
L4
P011C
L9
F2
F
G
H2
5/7
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