MX69V28F64
128M-BIT [8M x 16-bit] CMOS 1.8 Volt-only
1. FEATURES
Characteristics
Burst Length
•
Burst Mode - Continuous linear
Sector Architecture
Program/Erase Cycles
• 100,000 cycles typical
Data Retention
• 20 years
• Linear burst length - 8/16 word with wrap around
• Multi-bank Architecture (8 banks)
• Read while write operation
• Four 16 Kword sectors on top/ bottom of address
range
• 127 sectors are 64 KWord sectors
Hardware Features
• Supports multiplexing data and address for reduced
I/O count.
• A15–A0 multiplexed as Q15–Q0 Sector Architecture
Hardware Sector Protection
• All sectors locked when ACC = VIL
Power Supply Operations
• 1.8V for read, program and erase operations (1.70V
to 1.95V)
• Deep power down mode
Package
Performance
High Performance
• 30us - Word programming time
• 7.5us - Effective word programming time utilizing a
32 word Write Buffer at VCC level
• 2.5us - Effective word programming time of utilizing
a 32 word Write Buffer at ACC level
• 56-Ball Thin FBGA (Fine-Pitch Ball Grid Array)
• REACH SVHC Free and RoHS Compliant
Handshaking Feature
•
Allows system to determine the read operation
of burst data with minimum possible latency by
monitoring RDY.
Sector Erase Time
• 500ms for 16 Kword sectors
• 1000ms for 64 Kword sectors
Read Access Time
• Burst access time: 7ns (at industrial temperature
range)
• Asynchronous random access time: 80ns
• Synchronous random access time: 75ns
Secure Silicon Sector Region
• 128 words for the factory & customer secure silicon
sector
Power Dissipation
• Typical values: 8 bits switching,
CL = 10 pF at 108 MHz, CIN excluded
• 20mA for Continuous burst read mode
• 30mA for Program/Erase Operations (max.)
• 30uA for Standby mode
P/N:PM1751
REV. 1.3, JUL. 22, 2013
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