Any frequency between 1 and 80 MHz accurate to 6 decimal places
100% pin-to-pin drop-in replacement to quartz-based (VC)TCXO
Frequency stability as low as ±5 ppm. Contact SiTime for tighter
stability options
Ultra low phase jitter: 0.5 ps (12 kHz to 20 MHz)
Voltage control option with pull range from ±12.5 ppm to ±50 ppm
LVCMOS compatible output with SoftEdge
™
option for EMI reduction
Voltage control, standby, output enable or no connect modes
Standard 4-pin packages: 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mm
Outstanding silicon reliability of 2 FIT, 10 times better than quartz
Pb-free, RoHs and REACH compliant
WiFi, 3G, LTE, SDI, Ethernet, SONET, DSL
Telecom, networking, smart meter, wireless, test instrumentation
Electrical Characteristics
Parameter
Output Frequency Range
Initial Tolerance
Stability Over Temperature
Symbol
f
F_init
F_stab
Min.
1
-1
-5
Typ.
–
–
–
Max.
80
1
+5
Unit
MHz
ppm
ppm
At 25°C after two reflows
Over operating temperature range at rated nominal power
supply voltage and load. (see
ordering codes on page 6)
Contact SiTime for tighter stability options.
Supply Voltage
Output Load
First year Aging
10-year Aging
Operating Temperature Range
Supply Voltage
T_use
Vdd
F_vdd
F_load
F_aging
–
–
-2.5
-4.0
-20
-40
1.71
2.25
2.52
2.70
2.97
Pull Range
Upper Control Voltage
Control Voltage Range
Control Voltage Input Impedance
Frequency Change Polarity
Control Voltage -3dB Bandwidth
Current Consumption
OE Disable Current
Standby Current
Duty Cycle
LVCMOS Rise/Fall Time
SoftEdge™ Rise/Fall Time
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
VOH
VOL
VIH
VIL
Z_in
PR
VC_U
VC_L
Z_vc
–
V_BW
Idd
I_OD
I_std
DC
Tr, Tf
–
–
–
–
–
–
–
45
–
90%
–
70%
–
–
Vdd-0.1
–
100
50
0.1
–
–
–
–
1.8
2.5
2.8
3.0
3.3
±12.5, ±25, ±50
–
–
–
Positive slope
–
31
29
–
–
–
–
–
1.5
–
–
–
–
100
8
33
31
31
30
70
10
55
2
–
10%
–
30%
250
–
0.1
–
–
–
+2.5
+4.0
+70
+85
1.89
2.75
3.08
3.3
3.63
ppb
ppm
ppm
ppm
°C
°C
V
V
V
V
V
ppm
V
V
k
–
kHz
mA
mA
mA
mA
µA
µA
%
ns
ns
Vdd
Vdd
Vdd
Vdd
k
No load condition, f = 20 MHz, Vdd = 2.5V, 2.8V or 3.3V.
No load condition, f = 20 MHz, Vdd = 1.8V.
Vdd = 2.5V, 2.8V or 3.3V, OE = GND, output is Weakly Pulled Down
Condition
±10% Vdd (±5% for Vdd = 1.8V)
15 pF ±10% of load
25°C
25°C
Extended Commercial
Industrial
Contact SiTime for any other supply voltage options.
All Vdds. Voltage at which maximum deviation is guaranteed.
Vdd = 1.8 V. OE = GND, output is Weakly Pulled Down
Vdd = 2.5V, 2.8V or 3.3V, ST = GND, output is Weakly Pulled Down.
Vdd = 1.8V. ST = GND, output is Weakly Pulled Down.
All Vdds
LVCMOS option. Default rise/fall time, All Vdds, 10% - 90% Vdd.
SoftEdge™ option. Frequency and supply voltage dependent.
OH = -7 mA, IOL = 7 mA, (Vdd = 3.3V, 3.0V)
IOH = -4 mA, IOL = 4 mA, (Vdd = 2.8V, 2.5V)
IOH = -2 mA, IOL = 2 mA, (Vdd = 1.8V)
Pin 1, OE or ST
Pin 1, OE or ST
SoftEdge™ Rise/Fall Time Table
SiTime Corporation
Rev. 1.0
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised November 12, 2015
SiT5001
1-80 MHz MEMS TCXO and VCTCXO
The Smart Timing Choice
The Smart Timing Choice
Electrical Characteristics (continued)
Parameter
Startup Time
OE Enable/Disable Time
Resume Time
RMS Period Jitter
RMS Phase Jitter (random)
Symbol
T_start
T_oe
T_resume
T_jitt
T_phj
Min.
–
–
–
–
–
–
Typ.
–
–
6
1.7
1.7
0.5
Max.
10
150
10
2
2
1
Unit
ms
ns
ms
ps
ps
ps
Condition
Measured from the time Vdd reaches its rated minimum value
f = 80 MHz. For other frequencies, T_oe = 100 ns + 3 cycles
Measured from the time ST pin crosses 50% threshold
f = 10 MHz, Vdd = 2.5V, 2.8V or 3.3V
f = 10 MHz, Vdd = 1.8V
f = 10 MHz, Integration bandwidth = 12 kHz to 20 MHz, All Vdds
Note:
1. All electrical specifications in the above table are measured with 15pF output load, Contact SiTime for higher drive options.
Pin Configuration
Pin
Symbol
V control
Output
Enable
1
VC/OE/ST/NC
Standby
NC
2
3
4
GND
CLK
VDD
Power
Output
Power
Voltage control
H or Open
[2]
: specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[2]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
No connect (input receiver off)
Electrical and case ground
Oscillator output
Power supply voltage
GND
2
3
Functionality
Top View
VC/OE/ST
1
4
VDD
OUT
Note:
2. A pull-up resistor of <10 k between OE/ ST pin and Vdd is recommended in high noise environment when the device operates in OE/ST mode.
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Min.
-65
-0.5
–
–
Max.
150
4
2000
260
Unit
°C
V
V
°C
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.0
Page 2 of 7
www.sitime.com
SiT5001
1-80 MHz MEMS TCXO and VCTCXO
The Smart Timing Choice
The Smart Timing Choice
Timing Diagram
90% Vdd, 2.5/2,8/3.3V devices
Vdd
95% Vdd, 1.8V devices
Vdd
Pin 4 Voltage
50% Vdd
T_resume
CLK Output
CLK Output
ST Voltage
T_start
T_start: Time to start from power-off
T_resume: Time to resume from ST
(ST/OE Mode)
(ST Mode Only)
Phase Noise Plot
Phase Noise, 10M Hz carrier, 3.3V, LVCM OS output, TCXO
-100
-110
-120
-130
-140
-150
-160
-170
3
10
Integrated random phase jitter (RM S, 12kHz-5M Hz): 0.52ps
Phase Noise (dBc/Hz)
10
4
10
Frequency O ffset (Hz)
5
10
6
Rev. 1.0
Page 3 of 7
www.sitime.com
SiT5001
1-80 MHz MEMS TCXO and VCTCXO
The Smart Timing Choice
The Smart Timing Choice
SoftEdge™ Option
The SoftEdge™ output is available as a standard option for the SiT500x family of MEMS (VC)TCXOs. It is typically used for EMI
reduction similar to that of the clipped sinewave output common to many quartz based TCXOs.
In the SoftEdge™ mode, the slower rise/fall edges of the output waveform reduce the higher clock harmonics in a digital clock
signal, minimizing EMI radiation at these harmonics. The table below show the actual rise/fall time in relation to the desired
output frequency and the supply voltage with a 10 k / 10pF load. Rail-to-rail swing of the output is maintained for these
supported frequencies.
Rise/Fall Time for SoftEdge™ Option
Parameter
Rise/Fall Time
Symbol
Tr, Tf
Min.
4.0
2.5
1.5
1.5
Typ.
6.5
4.0
3.5
2.5
Max.
9.5
6.0
5.0
4.5
Unit
ns
ns
ns
ns
Condition
1-26 MHz, 1.8V, 3.0 and 3.3V, MHz 10k and 10 pF, 20%-80% Vd
1-26 MHz, 2.5V and 2.8V, MHz 10k and 10 pF, 20%-80% Vdd
26-50 MHz, 1.8V, 3.0V and 3.3V, MHz 10k and 10 pF, 20%-80% Vdd
26-50 MHz, 2.5V and 2.8V, MHz 10k and 10 pF, 20%-80% Vdd
SoftEdge™ Waveform Examples and Corresponding Harmonics Reduction
Figures below illustrate the harmonic power reduction as the rise/fall times are slowed from the standard squarewave output to
that of the SoftEdge™ output. In general, the 1.8V device shows the lowest harmonics and provides best EMI performance
comparing to devices with higher operating voltages.
LVCMOS and SoftEdge™ Outputs,
VDD = 3.3V
SoftEdge
LVCMOS
3.5
20
Odd Harmonic Power Comparison for LVCMOS and SoftEdge™ Outputs,
VDD = 3.3V
SoftEdge
LVCMOS
3
10
Harmonic Power (dbm)
2.5
0
-10dBm
Amplitude (V)
2
-10
1.5
-20
1
-24.4dbm
-30
0.5
0
-40
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
0
2
4
6
8
10
12
14
16
18
20
Time (ns)
Harmonic Number
LVCMOS and SoftEdge Outputs,
VDD = 1.8V
SoftEdge
LVCMOS
20
Odd Harmonic Power Comparison for LVCMOS and SoftEdge Outputs,
VDD = 1.8V
SoftEdge
LVCMOS
10
Harmonic Power (dbm)
Amplitude ( 0.5V/Div )
0
-10
-17 dBm
-20
-22
dBm
-30
-40
Time ( 20ns/Div )
0
2
4
6
8
10
12
14
16
18
20
Harmonic Number
LVCMOS and SoftEdge Outputs,
VDD = 2.5V
SoftEdge
LVCMOS
20
Odd Harmonic Power Comparison for LVCMOS and SoftEdge Outputs,
VDD = 2.5V
SoftEdge
LVCMOS
10
Harmonic Power (dbm)
Amplitude( 0.5V/Div)
0
-11 dBm
-10
-20
-20 dBm
-30
-40
0
2
4
6
8
10
12
14
16
18
20
Time (20 ns/Div)
Harmonic Number
Rev. 1.0
Page 4 of 7
www.sitime.com
SiT5001
1-80 MHz MEMS TCXO and VCTCXO
The Smart Timing Choice
The Smart Timing Choice
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
[3]
2.7 x 2.4 x 0.75 mm (100% compatible with 2.5 x 2. 0 mm footprint)
Recommended Land Pattern (Unit: mm)
[4]
YXXXX
3.2 x 2.5 x 0.75 mm
2.2
#4
3.2 ± 0.05
#4
#3
#3
2.1
2.5 ± 0.05
0.9
0.7
YXXXX
#1
#2
1.9
#2
#1
0.75 ± 0.05
0.9
1.4
5.0 x 3.2 x 0.75 mm
2.54
5.0 ± 0.05
#4
#3
#3
2.39
#4
3.2 ± 0.05
0.8
1.1
YXXXX
#1
#2
2.2
0.75 ± 0.05
#2
#1
1.15
1.5
7.0 x 5.0 x 0.90 mm
7.0 ± 0.05
5.08
5.08
5.0 ± 0.05
2.6
YXXXX
1.1
3.81
0.90 ± 0.10
1.4
2.2
Notes:
3. Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.
卡巴斯基的安全研究人员称其发现了如何攻击Intel微处理器的远程攻击代码，据传，这一代码可以通过TCP/IP包和JavaScript代码到达用户系统。 目前受影响的系统包括Windows XP，Vista，Windows Server 2003，Windows Server 2008，Linux甚至是BSD和Mac。但所幸大多数错误可以由Intel和BIOS厂商联合进行修复。 卡...[详细]
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