Si102x/3x
Ultra Low Power, 64/32 kB, 10-Bit ADC
MCU with Integrated 240–960 MHz EZRadioPRO
®
Transceiver
Ultra Low Power at 3.6V
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130 µA/MHz IBAT; dc-dc enabled
110 nA sleep current with data retention; POR monitor enabled
400 nA sleep current with smaRTClock (internal LFO)
700 nA sleep current with smaRTClock (external XTAL)
2 µs wake-up from any sleep mode
Up to 75 ksps 12-bit mode or 300 ksps 10-bit mode
External pin or internal VREF (no external capacitor required)
On-chip PGA allows measuring voltages up to twice the reference
voltage
Autonomous burst mode with 16-bit automatic averaging
accumulator
Integrated temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Up to ±500 µA; source and sink capability
Enhanced resolution via PWM interpolation
Supports up to 128 segments (32x4)
Integrated charge pump for contrast control
DC-DC buck converter allows dynamic voltage scaling for
maximum efficiency (250 mW output)
Sleep-mode pulse accumulator with programmable switch
de-bounce and pull-up control interfaces directly to metering sen-
sor
Dedicated Packet Processing Engine (DPPE) includes hardware
AES, DMA, CRC, and encoding blocks for acceleration of wireless
protocols
Manchester and 3 out of 6 encoder hardware for power efficient
implementation of the wireless M-bus specification
®
Frequency range = 240–960 MHz
Sensitivity = –121 dBm
FSK, GFSK, and OOK modulation
Max output power = +20 dBm or +13 dBm
12-Bit; 16 Ch. Analog-to-Digital Converter
RF power consumption
18.5 mA receive
18 mA @ +1 dBm transmit
30 mA @ +13 dBm transmit
85 mA @ +20 dBm transmit
Data rate = 0.123 to 256 kbps
Auto-frequency calibration (AFC)
Antenna diversity and transmit/receive switch control
Programmable packet handler
TX and RX 64-byte FIFOs
Frequency hopping capability
On-chip crystal tuning
Pipelined instruction architecture; executes 70% of instructions in 1
or 2 system clocks
Up to 128 kB Flash; In-system programmable; Full read/write/erase
functionality over the entire supply range
Up to 8 kB internal data RAM
53 port I/O; All 5 V tolerant with high sink
current and programmable drive strength
Hardware SMBus™ (I2C™ compatible), 2 x SPI™, and UART
serial ports available concurrently
Four general-purpose 16-bit counter/timers
Programmable 16-bit counter/timer array with six capture/compare
modules and watchdog timer
Precision internal oscillators: 24.5 MHz with ±2% accuracy sup-
ports UART operation; spread-spectrum mode for reduced EMI
Low power internal oscillator: 20 MHz
External oscillator: Crystal, RC, C, CMOS clock
smaRTClock oscillator: 32.768 kHz crystal or 16.4 kHz internal
LFO with three independent alarms
On-chip debug circuitry facilitates full-speed, non-intrusive, in-sys-
tem debug (no emulator required)
Provides 4 breakpoints, single stepping
–85 pin LGA (6 x 8 mm)
High-Speed 8051 µC Core
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Memory
Two Low Current Comparators
Internal 6-Bit Current Reference
Integrated LCD Controller (Si102x Only)
Metering-Specific Peripherals
Digital Peripherals
Clock Sources
On-Chip Debug
EZRadioPRO Transceiver
Packages
Power On
Reset/PMU
Wake
Reset
CIP-51 8051
Controller Core
128/64/32/16 kByte
ISP Flash Program
Memory
256 Byte SRAM
8192/4096 Byte XRAM
DMA
Analog
Power
Port I/O Configuration
Digital Peripherals
UART
Timers
0/1/2/3
PCA/
WDT
SMBus
SPI 0
Crossbar Control
LCD (4x32)
Port 0-1
Drivers
Port 2
Drivers
16
4
32
P0.0...P1.7
P2.4...P2.7
P3.0...P6.7
P7.0/C2D
C2CK/RST
Debug /
Programming
Hardware
C2D
Priority
Crossbar
Decoder
Port 3-6
Drivers
Port 7
Driver
VBAT
VDC
VBAT
VDD
CRC
Engine
AES
Engine
Encoder
RF XCVR
(240-960 MHz,
+20/+13 dBm)
VCO
VREG
Digital
Power
PA
TX
AGC
LNA
Mixer
PGA
VBATDC
IND
GNDDC
DC/DC Buck
Converter
Precision
24.5 MHz
Oscillator
LCD Charge
Pump
XTAL1
XTAL2
Low Power
20 MHz
Oscillator
External
Oscillator
Circuit
Enhanced
smaRTClock
Oscillator
SYSCLK
SFR
Bus
EMIF
Pulse Counter
EZRadioPro SPI 1
RXp
RXn
CAP
Analog Peripherals
Internal
VREF
External
VREF
A
M
U
X
VDD
VREF
Temp
Sensor
GND
CP0, CP0A
CP1, CP1A
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ADC
Digital
Modem
Delta
Sigma
Modulator
Digital
Logic
GND
XTAL3
XTAL4
12-bit
75ksps
ADC
3
SDN
nIRQ
GPIOx
XOUT
XIN
System Clock
Configuration
30 MHz
Comparators
Rev. 1.0 2/13
Copyright © 2013 by Silicon Laboratories
Si102x/3x
Si102x/3x
Table of Contents
1. System Overview ..................................................................................................... 25
1.1. Typical Connection Diagram ............................................................................. 28
1.2. CIP-51™ Microcontroller Core .......................................................................... 29
1.2.1. Fully 8051 Compatible .............................................................................. 29
1.2.2. Improved Throughput................................................................................ 29
1.2.3. Additional Features ................................................................................... 29
1.3. Port Input/Output ............................................................................................... 30
1.4. Serial Ports ........................................................................................................ 31
1.5. Programmable Counter Array............................................................................ 31
1.6. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power
Burst Mode.......................................................................................................... 32
1.7. Programmable Current Reference (IREF0)....................................................... 33
1.8. Comparators...................................................................................................... 33
2. Ordering Information ............................................................................................... 35
3. Pinout and Package Definitions ............................................................................. 36
3.1. LGA-85 Package Specifications ........................................................................ 45
3.1.1. Package Drawing ...................................................................................... 45
3.1.2. Land Pattern.............................................................................................. 47
4. Electrical Characteristics ........................................................................................ 48
4.1. Absolute Maximum Specifications..................................................................... 48
4.2. MCU Electrical Characteristics .......................................................................... 49
4.3. EZRadioPRO
®
Peripheral Electrical Characteristics......................................... 70
5. SAR ADC with 16-bit Auto-Averaging Accumulator and Autonomous Low Power
Burst Mode ................................................................................................................... 77
5.1. Output Code Formatting .................................................................................... 77
5.2. Modes of Operation ........................................................................................... 79
5.2.1. Starting a Conversion................................................................................ 79
5.2.2. Tracking Modes......................................................................................... 79
5.2.3. Burst Mode................................................................................................ 81
5.2.4. Settling Time Requirements...................................................................... 82
5.2.5. Gain Setting .............................................................................................. 82
5.3. 8-Bit Mode ......................................................................................................... 83
5.4. 12-Bit Mode ....................................................................................................... 83
5.5. Low Power Mode............................................................................................... 84
5.6. Programmable Window Detector....................................................................... 90
5.6.1. Window Detector In Single-Ended Mode .................................................. 92
5.6.2. ADC0 Specifications ................................................................................. 93
5.7. ADC0 Analog Multiplexer .................................................................................. 94
5.8. Temperature Sensor.......................................................................................... 96
5.8.1. Calibration ................................................................................................. 96
5.9. Voltage and Ground Reference Options ........................................................... 99
5.10. External Voltage Reference........................................................................... 100
5.11. Internal Voltage Reference............................................................................ 100
Rev. 1.0
3
Si102x/3x
5.12. Analog Ground Reference............................................................................. 100
5.13. Temperature Sensor Enable ......................................................................... 100
5.14. Voltage Reference Electrical Specifications .................................................. 101
6. Programmable Current Reference (IREF0).......................................................... 102
6.1. PWM Enhanced Mode..................................................................................... 102
6.2. IREF0 Specifications ....................................................................................... 103
7. Comparators........................................................................................................... 104
7.1. Comparator Inputs........................................................................................... 104
7.2. Comparator Outputs ........................................................................................ 105
7.3. Comparator Response Time ........................................................................... 106
7.4. Comparator Hysterisis ..................................................................................... 106
7.5. Comparator Register Descriptions .................................................................. 107
7.6. Comparator0 and Comparator1 Analog Multiplexers ...................................... 111
8. CIP-51 Microcontroller........................................................................................... 114
8.1. Instruction Set.................................................................................................. 115
8.1.1. Instruction and CPU Timing .................................................................... 115
8.2. CIP-51 Register Descriptions .......................................................................... 120
9. Memory Organization ............................................................................................ 123
9.1. Program Memory............................................................................................. 123
9.1.1. MOVX Instruction and Program Memory ................................................ 126
9.2. Data Memory ................................................................................................... 126
9.2.1. Internal RAM ........................................................................................... 127
9.2.2. External RAM .......................................................................................... 127
10. External Data Memory Interface and On-Chip XRAM ....................................... 128
10.1. Accessing XRAM........................................................................................... 128
10.1.1. 16-Bit MOVX Example .......................................................................... 128
10.1.2. 8-Bit MOVX Example ............................................................................ 128
10.2. Configuring the External Memory Interface (EMIF) ....................................... 129
10.3. Port Configuration.......................................................................................... 129
10.4. Multiplexed and Non-Multiplexed Selection................................................... 133
10.4.1. Multiplexed Configuration...................................................................... 133
10.4.2. Non-Multiplexed Configuration.............................................................. 133
10.5. Memory Mode Selection................................................................................ 134
10.5.1. Internal XRAM Only .............................................................................. 135
10.5.2. Split Mode without Bank Select............................................................. 135
10.5.3. Split Mode with Bank Select.................................................................. 135
10.5.4. External Only......................................................................................... 135
10.6. Timing .......................................................................................................... 136
10.6.1. Non-Multiplexed Mode .......................................................................... 138
10.6.2. Multiplexed Mode .................................................................................. 141
11. Direct Memory Access (DMA0)........................................................................... 145
11.1. DMA0 Architecture ........................................................................................ 146
11.2. DMA0 Arbitration ........................................................................................... 147
11.2.1. DMA0 Memory Access Arbitration ........................................................ 147
11.2.2. DMA0 Channel Arbitration .................................................................... 147
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Rev. 1.0
Si102x/3x
11.3. DMA0 Operation in Low Power Modes ......................................................... 147
11.4. Transfer Configuration................................................................................... 148
12. Cyclic Redundancy Check Unit (CRC0)............................................................. 159
12.1. 16-bit CRC Algorithm..................................................................................... 159
12.3. Preparing for a CRC Calculation ................................................................... 162
12.4. Performing a CRC Calculation ...................................................................... 162
12.5. Accessing the CRC0 Result .......................................................................... 162
12.6. CRC0 Bit Reverse Feature............................................................................ 166
13. DMA-Enabled Cyclic Redundancy Check Module (CRC1)............................... 167
13.1. Polynomial Specification................................................................................ 167
13.2. Endianness.................................................................................................... 168
13.3. CRC Seed Value ........................................................................................... 169
13.4. Inverting the Final Value................................................................................ 169
13.5. Flipping the Final Value ................................................................................. 169
13.6. Using CRC1 with SFR Access ...................................................................... 170
13.7. Using the CRC1 module with the DMA ......................................................... 170
14. Advanced Encryption Standard (AES) Peripheral ............................................ 174
14.1. Hardware Description .................................................................................... 175
14.1.1. AES Encryption/Decryption Core .......................................................... 176
14.1.2. Data SFRs............................................................................................. 176
14.1.3. Configuration SFRs............................................................................... 177
14.1.4. Input Multiplexer.................................................................................... 177
14.1.5. Output Multiplexer ................................................................................. 177
14.1.6. Internal State Machine .......................................................................... 177
14.2. Key Inversion................................................................................................. 178
14.2.1. Key Inversion using DMA...................................................................... 179
14.2.2. Key Inversion using SFRs..................................................................... 180
14.2.3. Extended Key Output Byte Order.......................................................... 181
14.2.4. Using the DMA to unwrap the extended Key ........................................ 182
14.3. AES Block Cipher .......................................................................................... 183
14.4. AES Block Cipher Data Flow......................................................................... 184
14.4.1. AES Block Cipher Encryption using DMA ............................................. 185
14.4.2. AES Block Cipher Encryption using SFRs ............................................ 186
14.5. AES Block Cipher Decryption........................................................................ 187
14.5.1. AES Block Cipher Decryption using DMA............................................. 187
14.5.2. AES Block Cipher Decryption using SFRs............................................ 188
14.6. Block Cipher Modes ...................................................................................... 189
14.6.1. Cipher Block Chaining Mode................................................................. 189
14.6.2. CBC Encryption Initialization Vector Location....................................... 191
14.6.3. CBC Encryption using DMA .................................................................. 191
14.6.4. CBC Decryption .................................................................................... 194
14.6.5. Counter Mode ....................................................................................... 197
14.6.6. CTR Encryption using DMA .................................................................. 199
15. Encoder/Decoder ................................................................................................. 206
15.1. Manchester Encoding.................................................................................... 207
Rev. 1.0
5
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