NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX8MDQLQCEC
Rev. 1, 10/2018
MIMX8MQ7DVAJZAA
MIMX8MQ6DVAJZAA
MIMX8MD7DVAJZAA
MIMX8MD6DVAJZAA
MIMX8MQ5DVAJZAA
MIMX8MQ7DVAJZAB
MIMX8MQ6DVAJZAB
MIMX8MD7DVAJZAB
MIMX8MD6DVAJZAB
MIMX8MQ5DVAJZAB
i.MX 8M Dual / 8M
QuadLite / 8M Quad
Applications Processors
Data Sheet for Consumer
Products
Package Information
Plastic Package
FBGA 17 x 17 mm, 0.65 mm pitch
Ordering Information
See
Table 2 on page 6
1
i.MX 8M Dual / 8M QuadLite
/ 8M Quad introduction
1. i.MX 8M Dual / 8M QuadLite / 8M Quad introduction . . . 1
1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6
2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1. Recommended connections for unused interfaces 12
3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 13
3.2. Power supplies requirements and restrictions . . . 25
3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 27
3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5. I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . 30
3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 32
3.7. Output buffer impedance parameters . . . . . . . . . 35
3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 37
3.9. External peripheral interface parameters . . . . . . 38
4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 74
4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 74
4.2. Boot device interface allocation . . . . . . . . . . . . . . 75
5. Package information and contact assignments . . . . . . . 76
5.1. 17 x 17 mm package information . . . . . . . . . . . . 76
5.2. DDR pin function list for 17 x 17 mm package . . 96
6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors
represent NXP’s latest market of connected streaming
audio/video devices, scanning/imaging devices, and
various devices requiring high-performance, low-power
processors.
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors
feature advanced implementation of a quad Arm®
Cortex®-A53 core, which operates at speeds of up to
1.5 GHz. A general purpose Cortex®-M4 core processor
is for low-power processing. The DRAM controller
supports 32-bit/16-bit LPDDR4, DDR4, and DDR3L
memory. There are a number of other interfaces for
connecting peripherals, such as WLAN, Bluetooth, GPS,
displays, and camera sensors. The i.MX 8M Quad and
i.MX 8M Dual processors have hardware acceleration
for video playback up to 4K, and can drive the video
outputs up to 60 fps. Although the i.MX 8M QuadLite
processor does not have hardware acceleration for video
decode, it allows for video playback with software
decoders if needed.
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
Table 1. Features
Subsystem
Arm Cortex-A53 MPCore platform
Feature
Quad symmetric Cortex-A53 processors:
• 32 KB L1 Instruction Cache
• 32 KB L1 Data Cache
• Support L1 cache RAMs protection with parity/ECC
Support of 64-bit Armv8-A architecture:
• 1 MB unified L2 cache
• Support L2 cache RAMs protection with ECC
• Frequency of 1.5 GHz
Arm Cortex-M4 core platform
16 KB L1 Instruction Cache
16 KB L1 Data Cache
256 KB tightly coupled memory (TCM)
Connectivity
Two PCI Express Gen2 interfaces
Two USB 3.0/2.0 controllers with integrated PHY interfaces
Two Ultra Secure Digital Host Controller (uSDHC) interfaces
One Gigabit Ethernet controller with support for EEE, Ethernet AVB, and IEEE 1588
Four Universal Asynchronous Receiver/Transmitter (UART) modules
Four I
2
C modules
Three SPI modules
External memory interface
32/16-bit DRAM interface: LPDDR4-3200, DDR4-2400, DDR3L-1600
8-bit NAND-Flash
eMMC 5.0 Flash
SPI NOR Flash
QuadSPI Flash with support for XIP
GPIO and pin multiplexing
GPIO modules with interrupt capability
Input/output multiplexing controller (IOMUXC) to provide centralized pad control
On-chip memory
Boot ROM (128 KB)
On-chip RAM (128 KB + 32 KB)
Power management
Temperature sensor with programmable trip points
Flexible power domain partitioning with internal power switches to support efficient
power management
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1, 10/2018
2
NXP Semiconductors
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
Table 1. Features (continued)
Subsystem
Multimedia
Feature
Video Processing Unit:
• 4Kp60 HEVC/H.265 main, and main 10 decoder
• 4Kp60 VP9 decoder
• 4Kp30 AVC/H.264 decoder
• 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder
Graphic Processing Unit:
• 4 shader
• 267 million triangles/sec
• 1.6 Giga pixel/sec
• 32 GFLOPs 32-bit or 64 GFLOPs 16-bit
• Support OpenGL ES 1.1, 2.0, 3.0, 3.1, Open CL 1.2, and Vulkan
HDMI Display Interface:
• HDMI 2.0a supporting one display: resolution up to 4096 x 2160 at 60 Hz, support
HDCP 2.2 and HDCP 1.4
1
• 20+ Audio interfaces 32-bit @ 384 kHz fs, with Time Division Multiplexing (TDM)
support
• S/PDIF input and output
• Audio Return Channel (ARC) on HDMI
• Upscale HD graphics to 4K for display
• Downscale 4K video to HD for display
• Display Port
• Embedded Display Port
MIPI-DSI Display Interface:
• MIPI-DSI 4 channels supporting one display, resolution up to 1920 x 1080 at 60 Hz
• LCDIF display controller
• Output can be LCDIF output or DC display controller output
Audio:
• S/PDIF input and output
• Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and
codec/DSP interfaces, including one SAI with 16 Tx and 16 Rx channels, one SAI
with 8 Tx and 8 Rx channels, and three SAI with 2 Tx and 2 Rx channels
• One SAI for 8 Tx channels for HDMI output audio
• One S/PDIF input for HDMI ARC input
Camera inputs:
• Two MIPI-CSI2 camera inputs (4-lane each)
Security
Resource Domain Controller (RDC) supports four domains and up to eight regions
Arm TrustZone (TZ) architecture
On-chip RAM (OCRAM) secure region protection using OCRAM controller
High Assurance Boot (HAB)
Cryptographic acceleration and assurance (CAAM) module
Secure non-volatile storage (SNVS): Secure real-time clock (RTC)
Secure JTAG controller (SJC)
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1, 10/2018
NXP Semiconductors
3
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
Table 1. Features (continued)
Subsystem
System debug
Feature
Arm CoreSight debug and trace architecture
TPIU to support off-chip real-time trace
ETF with 4 KB internal storage to provide trace buffering
Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs
Cross Triggering Interface (CTI)
Support for 5-pin (JTAG) debug interface
1
Please contact the NXP sales and marketing team for order details on HDCP enable parts.
NOTE
The actual feature set depends on the part numbers as described in
Table 2.
Functions such as display and camera interfaces, and connectivity
interfaces, may not be enabled for specific part numbers.
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1, 10/2018
4
NXP Semiconductors
i.MX 8M Dual / 8M QuadLite / 8M Quad introduction
1.1
Block diagram
Figure 1
shows the functional modules in the i.MX 8M Dual / 8M QuadLite / 8M Quad processor system.
Security
TrustZone
DRM Ciphers
Secure Clock
eFuse Key Storage
Main CPU Platform
Quad Cortex-A53
32 KB I-cache
NEON
32 KB D-cache
FPU
Connectivity and I/O
1 GB Ethernet
(IEEE1588, EEE, and AVB)
S/PDIF Rx and Tx,
I2S/SAI x6
PCIe 2.0 x2 (1-lane, each)
1 MB L2 Cache
Random Number
USB 3.0/2.0 OTG x2
32 KB Secure RAM
Low Power, Security CPU
Cortex-M4
System Control
Smart DMA x2
Timer x3
16 KB I-cache
16 KB D-cache
256 KB TCM
HDMI 2.0a output
HDCP 2.2
MIPI DSI Display x1
MIPI CSI2 Capture x2
Multimedia
3D Graphics: 4 Shader
OpenGL/ES 3.1, CL 1.2, Vulkan
4Kp60 HEVC/H.265
4Kp60 VP9
4Kp30 H.264 Decoder and VP9
1080p60 MPEG-2, MPEG-4p2,
VC-1, VP8, RV9, AVS,
MJPEG, H.263 Decoder
External Memory
LPDDR4-3200
DDR4-2400
DDR3L-1600
UART x4, 5 Mbps
I2C x4, SPI x3
PWM x4
Watchdog x3
Temp Monitor
2x eMMC 5/SD 3
NAND CTL (BCH62)
Secure JTAG
Temperature Sensor
4Kp60 Display
QuadSPI (XIP)
Figure 1. i.MX 8M Dual / 8M QuadLite / 8M Quad system block diagram
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Data Sheet for Consumer Products, Rev. 1, 10/2018
NXP Semiconductors
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
