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JTAG-SMT2™ Programming Module for Xilinx
®
FPGAs
Revised November 21, 2017
This manual applies to the JTAG-SMT2 rev. D
Overview
The Joint Test Action Group (JTAG)-SMT2 is a compact, complete, and fully self-contained surface-mount
programming module for Xilinx field-programmable gate arrays (FPGAs). The module can be accessed directly from
all Xilinx Tools, including iMPACT,
Chipscope™,
eFuse, Vivado, and EDK. Users can load the module directly onto a
target board and reflow it like any other component.
The JTAG-SMT2 uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG
signals use high speed, 24mA, three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds of up
to 30MBit/sec. The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance,
except when actively driven during programming. The SMT2 module is CE certified and fully compliant with EU
RoHS and REACH directives. The module uses a standard Type-A to Micro-USB cable available for purchase from
Digilent, Inc.
Features include:
•
•
•
•
•
•
GND 1
TCK 2
TDI 3
11 Vdd (3.3V)
10 GND
9 VREF
•
•
•
•
•
TMS 4
5
GPIO0
6 GPIO1
7
GPIO2
8 TDO
JTAG-SMT2.
Small, complete, all-in-one JTAG programming/debugging
solution for Xilinx FPGAs
Compatible with all Xilinx Tools
Compatible with IEEE 1149.7-2009 Class T0
–
Class T4
(includes 2-Wire JTAG)
GPIO pin allows debugging software to reset the processor
core of Xilinx’s Zynq®
platform
Single 3.3V supply
Separate Vref drives JTAG signal voltages; Vref can be any
voltage between 1.8V and 5V.
High-Speed USB2 port that can drive JTAG/SPI bus at up to
30Mbit/sec (frequency settable by user)
SPI programming solution (modes 0 and 2 up to 30Mbit/sec,
modes 1 and 3 up to 2Mbit/sec)
Uses micro-AB USB2 connector
Small form-factor surface-mount module can be directly
loaded on target boards
A similar circuit is available as a stand-alone programming
cable; see Digilent’s JTAG-HS2.
Users can connect JTAG signals directly to the corresponding FPGA signals, as shown in Fig. 1. For best results,
mount the module adjacent to the edge of the host PCB over a ground plane. Although users may run signal traces
The JTAG-SMT2
on top of the host PCB beneath the SMT2, Digilent recommends keeping the area immediately beneath the SMT2
clear.
Note: Keep the impedance between the SMT2 and FPGA below 100 Ohms to operate the JTAG at maximum speed.
DOC#: 502-251
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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JTAG -SMT2™ Programming Module for Xilinx® FPGAs
3.3V
Vdd
VREF
USB2
Port
TCK
TDO
11
9
3.3V
V
IO
Vdd
VIO
TMS
TCK
TDI
TDO
11
9
V
IO
VREF
USB2
Port
TCK
TDO
VIO
SS
SCK
MOSI
MISO
TMS
4
2
TMS
4
2
TDI
3
8
1
TDI
3
8
1
GND
JTAG-SMT2
GND
FPGA
GND
JTAG-SMT2
GND
FPGA
Figure 1. JTAG-SMT2 port connections.
The SMT2 improves upon the SMT1 with the addition of three general purpose IO pins (GPIO0
–
GPIO2) and
support for interfacing IEEE 1149.7-2009 JTAG targets in both 2 and 4-wire modes.
Figure 2. SMT2 SPI port connections.
In addition to supporting JTAG, the JTAG-SMT2 also features eight highly configurable Serial Peripheral Interface
(SPI) ports that allow communication with virtually any SPI peripheral (see Fig. 2). All eight SPI ports share the
same SCK, MOSI, and MISO pins, so users may enable only one port at any given time. Table 1 summarizes the
features supported by each port. The HS2 supports SPI modes 0, 1, 2, and 3.
Chip Select
Signal
Port
Number
0
TMS/CS0
1
SPI
Mode
0
2
0
1
2
3
0
2
0
1
2
3
0
2
0
1
2
3
0
2
0
1
2
3
Shift
LSB
First
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Shift
MSB
First
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Selectable
SCK
Frequency
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Max SCK
Frequency
30 MHz
30 MHz
2.066 MHz
2.066 MHz
2.066 MHz
2.066 MHz
30 MHz
30 MHz
2.066 MHz
2.066 MHz
2.066 MHz
2.066 MHz
30 MHz
30 MHz
2.066 MHz
2.066 MHz
2.066 MHz
2.066 MHz
30 MHz
30 MHz
2.066 MHz
2.066 MHz
2.066 MHz
2.066 MHz
Min SCK
Frequency
8 KHz
8 KHz
485 KHz
485 KHz
485 KHz
485 KHz
8 KHz
8 KHz
485 KHz
485 KHz
485 KHz
485 KHz
8 KHz
8 KHz
485 KHz
485 KHz
485 KHz
485 KHz
8 KHz
8 KHz
485 KHz
485 KHz
485 KHz
485 KHz
Inter-byte
Delay
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
0
–
1000 µS
2
GPIO0/CS1
3
4
GPIO1/CS2
5
6
GPIO2/CS3
7
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Table 1. Supported features.
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JTAG -SMT2™ Programming Module for Xilinx® FPGAs
Note: The Xilinx Tools expect GPIO2/CS3 to be connected to the SRST_B pin on a Zynq chip. As a result, SPI ports 6
and 7 may not be used for SPI communication if the Xilinx Tools are going to be used to communicate with the
SMT2.
1
Software Support
In addition to working seamlessly with all Xilinx Tools, which includes iMPACT, ChipScope, eFuse, Vivado, and EDK,
Digilent’s Adept software and the Adept software development kit
(SDK) support the SMT2 module. For added
convenience, customers may freely download the SDK from Digilent’s website. This Adept software
includes a full-
featured programming environment and a set of public application programming interfaces (API) that allow user
applications to directly drive the JTAG chain.
With the Adept SDK, users can create custom applications that will drive JTAG ports on virtually any device. Users
may utilize the APIs provided by the SDK to create applications that can drive any SPI device supporting those
modes. Please see the Adept SDK reference manual for more information.
2
IEEE 1149.7-2009 Compatibility
The JTAG-HS2 supports several scan formats, including the JScan0-JScan3, MScan, and OScan0 - OScan7. It is
capable of communicating in 4-wire and 2-wire scan chains that consist of Class T0
–
T4 JTAG Target Systems (TS)
(see Figs. 3 & 4).
Host
+
JTAG-SMT2
(DTS)
TMS
TDI
TCK
TDO
TMS
TDI
TCK
TDO
Target
System 0
TMS
TDI
TCK
TDO
Target
System 1
TMS
TDI
TCK
TDO
Target
System N
Figure 3. 4-Wire series topology.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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JTAG -SMT2™ Programming Module for Xilinx® FPGAs
4-Wire Star Topology
TMS
TDI
TCK
TDO
TMSC
TDIC
Target
System 0
TCKC
TDOC
Host
+
JTAG-SMT2
(DTS)
2-Wire Star Topology
TMS
TDI
TCK
TDO
TMSC
TDIC
Target
TCKC System 0
TDOC
Host
+
JTAG-SMT2
(DTS)
TMSC
TDIC
Target
TCKC System 1
TDOC
TMSC
TDIC
Target
System 1
TCKC
TDOC
TMSC
TDIC
Target
TCKC System N
TDOC
TMSC
TDIC
Target
TCKC System N
TDOC
Figure 4. 4-Wire and 2-Wire star topology.
The IEEE 1149.7-2009 specification requires any device that functions as a debug and test system (DTS) to provide
a pull-up bias on the TMS and TDO pins. In order to meet this requirement, the JTAG-SMT2 features weak pull-ups
(100K ohm) on the TMS, TDI, TDO, and TCK signals. Though not required in the specifications, the pull-ups on the
TDI and TCK signals ensure that neither signal floats while another source is not driving them (see Fig. 5).
VREF
VREF
100K
100K
JtagEN
Output Pin
(TMS, TDI, TCK)
Input Pin
(TDO)
Figure 5. Pull-ups on TMS, TDI, TDO, and TCK signals.
Users should place a current limiting resistor between the TMS pin of the SMT2 and the TMSC pin of the TS when
using the JTAG-SMT2 to interface with an 1149.7 compatible TS. If a drive conflict occurs, this resistor should
prevent damage to components by limiting the amount of current flowing between the pins of each device. A 200
ohm resistor will limit the maximum current to 16.5mA when using a 3.3V reference (see Figs. 6 & 7). While this
level of resistance should be sufficient for most applications, the value of the resistor may need to be adjusted to
meet the requirements of the TS.
In most cases users can avoid a drive conflict by having applications that use the SMT2 communicate with the TS in
two-wire mode. Use the applications to reconfigure the TS to use the JScan0, JScan1, JScan2, or JScan3 scan
format prior to
disabling the SMT2’s JTAG port.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page
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JTAG -SMT2™ Programming Module for Xilinx® FPGAs
3.3V
VIO
VDD
VREF
TMS
JTAG-
SMT2
GND
TDI
TDO
TCK
VIO
200
VIO
TMSC
TDIC
TDOC
TCKC
1149.7
Target
System
GND
Figure 6. Adding a current limiting resistor.
3.3V
VIO
VDD
VREF
TMS
JTAG-
SMT2
GND
TDI
TDO
TCK
VIO
200
VIO
TMSC
TDIC
TDOC
TCKC
1149.7
Target
System
GND
Figure 7. 200 Ohm resistor limiting current flow.
The Adept SDK provides an example application that demonstrates how to communicate with a Class T4 TAP
controller using the MScan, OScan0, and OScan1 scan formats.
3
GPIO Pins
The JTAG-SMT2 has three general purpose IO pins (GPIO0, GPIO1, and GPIO2) that are useful for a variety of
different applications. Each pin features high speed, three-state input and output buffers. At power up, the JTAG-
SMT2 disables these output buffers and places the signals in a high-impedance state. Each signal remains in a
high-impedance state until a host application enables DPIO port 0 and configures the applicable pin as an output.
When the host application disables DPIO port 0, all GPIO pins revert to a high-impedance state. Weak pull-ups
(100K ohm) ensure that the GPIO signals do not float while not being actively driven (see Fig. 8).
VREF
100K
IO Pin
(GPIO0, GPIO1, GPIO2)
OEGPIOx
Figure 8. GPIO signals.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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