APEX 20K
Programmable Logic
Device Family
March 2004, ver. 5.1
Data Sheet
Features
■
■
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
–
MultiCore
TM
architecture integrating look-up table (LUT) logic,
product-term logic, and embedded memory
–
LUT logic used for register-intensive functions
–
Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
–
ESB implementation of product-term logic used for
combinatorial-intensive functions
High density
–
30,000 to 1.5 million typical gates (see
Tables 1
and
2)
–
Up to 51,840 logic elements (LEs)
–
Up to 442,368 RAM bits that can be used without reducing
available logic
–
Up to 3,456 product-term-based macrocells
Note (1)
EP20K100
263,000
Table 1. APEX 20K Device Features
Feature
Maximum
system
gates
Typical
gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O
pins
EP20K30E
113,000
EP20K60E
162,000
EP20K100E
263,000
EP20K160E
404,000
EP20K200
526,000
EP20K200E
526,000
30,000
1,200
12
24,576
192
128
60,000
2,560
16
32,768
256
196
100,000
4,160
26
53,248
416
252
100,000
4,160
26
53,248
416
246
160,000
6,400
40
81,920
640
316
200,000
8,320
52
106,496
832
382
200,000
8,320
52
106,496
832
376
Altera Corporation
DS-APEX20K-5.1
1
APEX 20K Programmable Logic Device Family Data Sheet
Table 2. Additional APEX 20K Device Features
Feature
Maximum system
gates
Typical gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum user I/O
pins
Note to
Tables 1
and
2:
(1)
Note (1)
EP20K400E
1,052,000
400,000
16,640
104
212,992
1,664
488
EP20K300E
728,000
300,000
11,520
72
147,456
1,152
408
EP20K400
1,052,000
400,000
16,640
104
212,992
1,664
502
EP20K600E
1,537,000
600,000
24,320
152
311,296
2,432
588
EP20K1000E EP20K1500E
1,772,000
1,000,000
38,400
160
327,680
2,560
708
2,392,000
1,500,000
51,840
216
442,368
3,456
808
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
Additional
Features
■
Designed for low-power operation
–
1.8-V and 2.5-V supply voltage (see
Table 3)
–
MultiVolt
TM
I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see
Table 3)
–
ESB offering programmable power-saving mode
Table 3. APEX 20K Supply Voltages
Feature
EP20K100
EP20K200
EP20K400
Device
EP20K30E
EP20K60E
EP20K100E
EP20K160E
EP20K200E
EP20K300E
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
1.8 V
1.8 V, 2.5 V, 3.3 V, 5.0 V
(1)
Internal supply voltage (V
CCINT
)
2.5 V
MultiVolt I/O interface voltage levels (V
CCIO
) 2.5 V, 3.3 V, 5.0 V
Note to
Table 3:
(1)
APEX 20KE devices can be 5.0-V tolerant by using an external resistor.
2
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
■
■
■
■
■
Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
–
Built-in low-skew clock tree
–
Up to eight global clock signals
–
ClockLock
®
feature reducing clock delay and skew
–
ClockBoost
®
feature providing clock multiplication and division
–
ClockShift
TM
programmable clock phase and delay shifting
Powerful I/O features
–
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG)
PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
–
Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
–
Bidirectional I/O performance (t
CO
+
t
SU
) up to 250 MHz
–
LVDS performance up to 840 Mbits per channel
–
Direct connection from I/O pins to local interconnect providing
fast
t
CO
and
t
SU
times for complex logic
–
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see
Table 3)
–
Programmable clamp to V
CCIO
–
Individual tri-state output enable control for each pin
–
Programmable output slew-rate control to reduce switching
noise
– Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
–
Pull-up on I/O pins before and during configuration
Advanced interconnect structure
–
Four-level hierarchical FastTrack
®
Interconnect structure
providing fast, predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
Advanced packaging options
–
Available in a variety of packages with 144 to 1,020 pins (see
Tables 4
through
7)
–
FineLine BGA
®
packages maximize board space efficiency
Advanced software support
–
Software design support and automatic place-and-route
provided by the Altera
®
Quartus
®
II development system for
3
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
–
–
–
–
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
Altera MegaCore
®
functions and Altera Megafunction Partners
Program (AMPP
SM
) megafunctions
NativeLink
TM
integration with popular synthesis, simulation,
and timing analysis tools
Quartus II SignalTap
®
embedded logic analyzer simplifies
in-system design evaluation by giving access to internal nodes
during device operation
Supports popular revision-control software packages including
PVCS, Revision Control System (RCS), and Source Code Control
System (SCCS )
Notes (1), (2)
Table 4. APEX 20K QFP, BGA & PGA Package Options & I/O Count
Device
144-Pin
TQFP
92
92
101
92
88
208-Pin
PQFP
RQFP
125
148
159
151
143
144
136
240-Pin
PQFP
RQFP
151
189
183
175
174
168
152
356-Pin BGA 652-Pin BGA 655-Pin PGA
EP20K30E
EP20K60E
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
196
252
246
271
277
271
376
408
502
488
488
488
488
502
4
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 5. APEX 20K FineLine BGA Package Options & I/O Count
Device
EP20K30E
EP20K60E
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
EP20K300E
EP20K400
EP20K400E
EP20K600E
EP20K1000E
EP20K1500E
Notes to
Tables 4
and
5:
(1)
(2)
Notes (1), (2)
672 Pin
1,020 Pin
144 Pin
93
93
93
324 Pin
128
196
252
246
484 Pin
316
382
376
376
408
502
(3)
488
(3)
508
(3)
508
(3)
588
708
808
(3)
I/O counts include dedicated input and clock pins.
APEX 20K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGA, and pin-grid array (PGA)
packages.
This device uses a thermally enhanced package, which is taller than the regular package. Consult the
Altera Device
Package Information Data Sheet
for detailed package size information.
Table 6. APEX 20K QFP, BGA & PGA Package Sizes
Feature
Pitch (mm)
Area (mm
2
)
Length
×
Width
(mm
×
mm)
144-Pin TQFP 208-Pin QFP 240-Pin QFP 356-Pin BGA 652-Pin BGA 655-Pin PGA
0.50
484
22
×
22
0.50
924
30.4
×
30.4
0.50
1,218
34.9
×
34.9
1.27
1,225
35
×
35
1.27
2,025
45
×
45
–
3,906
62.5
×
62.5
Table 7. APEX 20K FineLine BGA Package Sizes
Feature
Pitch (mm)
Area (mm )
Length
×
Width (mm
×
mm)
2
144 Pin
1.00
169
13
×
13
324 Pin
1.00
361
19
×
19
484 Pin
1.00
529
23
×
23
672 Pin
1.00
729
27
×
27
1,020 Pin
1.00
1,089
33
×
33
Altera Corporation
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
