Si5328

ITU-T G.8262 S

YNCHRONOUS

E

THE RN ET

J

ITTER

- A

TTENUATING

C

LO CK

M

U LT I P L I ER

Features



Fully-compliant with ITU-T

G.8262, EEC options 1 and 2.

Generates any frequency from

8 kHz to 808 MHz.

Ultra-low jitter clock outputs with

jitter generation as low as 0.3 ps

rms (12 kHz–20 MHz)

Integrated loop filter with

selectable loop bandwidth

(0.1 Hz; 1 to 10 Hz)

Dual clock inputs with manual or

automatically controlled hitless

switching

Dual clock outputs with

selectable signal format

(LVPECL, LVDS, CML, CMOS)



LOL, LOS, FOS alarm outputs



I

2

C or SPI programmable



On-chip voltage regulator for

2.5 ±10% or 3.3 V ±10%

operation



Small size: 6 x 6 mm 36-lead

QFN



Pb-free, ROHS compliant



Ordering Information:

See page 63.

Pin Assignments

CKOUT1–

CKOUT2+

CMODE

CKOUT2–

G.8262 Synchronous Ethernet,

EEC options 1 and 2



GbE/10GbE/100GbE

Synchronous Ethernet



Carrier Ethernet switches,

routers

GND

36 35 34 33 32 31 30 29 28

RST

NC

INT_C1B

C2B

VDD

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

CKIN1+

VDD

CKIN2–

NC

CKIN2+

CKIN1–

RATE0

RATE1

LOL

27 SDI

26 A2_SS

25 A1

CKOUT1+

24 A0

23 SDA_SDO

22 SCL

21 CS_CA

20 NC

19 NC

Applications

VDD

NC

Description

The Si5328 is a jitter-attenuating precision clock multiplier for

Synchronous Ethernet applications requiring sub 1 ps jitter performance

and ultra-low loop bandwidth. When combined with a low-wander, low-

jitter reference oscillator, the Si5328 meets all of the wander, MTIE,

TDEV, and other requirements listed in ITU-T G.8262/Y.1362. The Si5328

accepts two input clocks ranging from 8 kHz to 710 MHz and generates

two output clocks ranging from 8 kHz to 808 MHz. The two outputs are

divided down separately from a common source. The Si5328 can also

use the TCXO as a clock source for frequency synthesis. The device

provides virtually any frequency translation combination across this

operating range. The Si5328 input clock frequency and clock

multiplication ratio are programmable through an I

2

C or SPI interface. The

Si5328 is based on Silicon Laboratories' third-generation DSPLL

®

technology, which provides frequency synthesis and jitter attenuation in a

highly integrated PLL solution that eliminates the need for external VCXO

and loop filter components. The DSPLL loop bandwidth is digitally

programmable, providing jitter performance optimization at the application

level. Operating from a single 2.5 or 3.3 V supply, the Si5328 is ideal for

providing clock multiplication and jitter attenuation in high-performance,

Synchronous Ethernet timing applications.

XA

XB

GND

NC

GND

Pad

Rev. 1.0 7/13

NC

Si5328

Si5328

Functional Block Diagram

TCXO or Refclock

CKIN1

÷ N31

Hitless Switching

Mux

÷ N1_LS

CKOUT1

®

CKIN2

÷ N32

DSPLL

÷ N1_HS

÷ N2_LS

CKOUT2

Refclock

÷ N2

Loss of Signal/

Frequency Offset

Loss of Lock

VDD (2.5 or 3.3 V)

Signal Detect

Control

GND

I

2

C/SPI Port

Device Interrupt

Rate Select

Clock Select

2

Rev. 1.0

Si5328

T

ABLE

OF

C

ONTENTS

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1. External XAXB Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

7. Pin Descriptions: Si5328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

9. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11. Si5328 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Rev. 1.0

3

Si5328

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Ambient Temperature

Supply Voltage during

Normal Operation

Symbol

T

A

V

DD

3.3 V Nominal

2.5 V Nominal

Test Condition

Min

–40

2.97

2.25

Typ

25

3.3

2.5

Max

85

3.63

2.75

Unit

C

V

Note:

All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.

SIGNAL +

Differential I/Os V , V

OCM

ICM

SIGNAL –

V

ISE

, V

OSE

Single-Ended

Peak-to-Peak Voltage

(SIGNAL +) – (SIGNAL –)

V

ICM

, V

OCM

V

ID

,V

OD

t

Differential Peak-to-Peak Voltage

SIGNAL +

SIGNAL –

V

ID

= (SIGNAL+) – (SIGNAL–)

Figure 1. Differential Voltage Characteristics

80%

CKIN, CKOUT

20%

t

F

t

R

Figure 2. Rise/Fall Time Characteristics

4

Rev. 1.0

Si5328

Table 2. DC Characteristics

(V

DD

= 2.5 V ±10% or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter

Supply Current

1

Symbol

I

DD

Test Condition

LVPECL Format

808 MHz Out

Both CKOUTs Enabled

LVPECL Format

808 MHz Out

1 CKOUT Enabled

CMOS Format

25 MHz Out

Both CKOUTs Enabled

CMOS Format

25 MHz Out

1 CKOUT Enabled

Disable Mode

Min

—

Typ

251

Max

279

Unit

mA

—

217

243

mA

—

204

234

mA

—

194

220

mA

—

165

—

mA

CKINn Input Pins

2

Input Common Mode

Voltage (Input Thresh-

old Voltage)

Input Resistance

Single-Ended Input

Voltage Swing

(See Absolute Specs)

V

ICM

2.5 V ± 10%

3.3 V ± 10%

CKN

RIN

V

ISE

Single-ended

f

CKIN

< 212.5 MHz

See Figure 1.

f

CKIN

> 212.5 MHz

See Figure 1.

V

ID

f

CKIN

< 212.5 MHz

See Figure 1.

fCKIN > 212.5 MHz

See Figure 1.

1

1.1

20

0.2

0.25

0.2

0.25

—

40

—

1.7

1.95

60

—

V

k

V

PP

V

PP

V

PP

V

PP

Differential Input

Voltage Swing

(See Absolute Specs)

Notes:

1.

Current draw is independent of supply voltage

2.

No under- or overshoot is allowed.

3.

LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 312.5 MHz.

4.

This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family

Reference Manual for more details.

Rev. 1.0

5

参数名称	属性值
PLL	是
主要用途	以太网
输入	时钟
输出	CML，CMOS，LVDS，LVPECL
电路数	1
比率 - 输入:输出	2：2
差分 - 输入:输出	是/是
频率 - 最大值	808MHz
电压 - 电源	2.25 V ~ 3.63 V
工作温度	-40°C ~ 85°C
安装类型	表面贴装
封装/外壳	36-VFQFN 裸露焊盘
供应商器件封装	36-QFN（6x6）

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