电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

VSC8584XKS-14

产品描述4P Q/SGMII CU/FI 3E, 256, 4NS IN
产品类别半导体    模拟混合信号IC   
文件大小401KB,共2页
制造商Microsemi
官网地址https://www.microsemi.com
标准
下载文档 选型对比 全文预览

VSC8584XKS-14在线购买

供应商 器件名称 价格 最低购买 库存  
VSC8584XKS-14 - - 点击查看 点击购买

VSC8584XKS-14概述

4P Q/SGMII CU/FI 3E, 256, 4NS IN

文档预览

下载PDF文档
VSC8584
Quad-Port 10/100/1000BASE-T, 100/1000BASE-X PHY with Synchronous Ethernet, VeriTime™, Intellisec™, and QSGMII/ SGMII MAC
Enables network-wide Layer 2 MACsec encryption and preserves
nanosecond-level IEEE 1588v2 network timing accuracy with a
simple PHY upgrade.
The quad port VSC8584 GbE PHY with Intellisec and VeriTime is
ideal for securing cloud network applications including e-commerce,
databases, collaboration, smart grid, video, and enterprise or
government communications.
Intellisec enables a realistic and affordable Layer 2 MACsec
security solution. Intellisec is a patent-pending technology enabling
IEEE 802.1AE MACsec encryption end-to-end over any network,
including multi-operator and cloud-based networks, independent
of the network's awareness of security protocols. Intellisec is not
limited to traditional MACsec link-based box-to-box applications.
Likewise, Intellisec scales easily with the number of interfaces
delivering significant cost savings in network deployment.
VeriTime is Microsemi's patent-pending timing technology
that delivers the industry's most accurate IEEE 1588v2 timing
implementation down to 4 ns. Integration of MACsec with IEEE
1588v2 time stamping in the PHY is an efficient and low cost
method to protect data passing through the network while
maintaining highly accurate time of day (ToD). For these applications,
the device supports daisy-chaining of SPI interfaces for IEEE 1588v2
time stamping to reduce the number of pins required on a target
ASIC, SoC or FPGA.
VSC8584 supports Y.1731 OAM and MPLS-TP OAM for accurate
delay measurement and performance monitoring. In addition,
it includes dual recovered clock outputs for timing references
in Synchronous Ethernet solutions. Using Microsemi's Ring
Resiliency™ technology, the PHY switches between master and
slave timing without interrupting the 1000BASE-T link.
Ethernet Line Card
Linecard Control
Processor
Ethernet Port
VSC8584
Packet
Processing
Highlights
• Part of the world's first and only NIST FIPS197
128/256-bit MACsec-support family of GbE
PHYs
• 802.1AE-2006, 802.1AEbn-2011, and
802.1AEbw-2013 compliant
• Exclusive patented "Tag-in-the-Clear" and
"Flow-Based" technologies enable MACsec
to work in any IPv4 or IPv6-based network
capable of supporting VLANs and/or MPLS
• One-step and two-step VeriTime™ time
stamping over encapsulated links including
MPLS and PBB
• MPLS and Ethernet Y.1731 OAM
• EcoEthernet™ 2.0 green technology
• Supports clause 45 MDIO register access
• Enhanced SPI interface supports high port
count IEEE 1588v2 applications
Applications
• Wireless backhaul systems
• Carrier Ethernet cellular base systems
• Industrial automation systems
• Secure data center to data center interconnects
System Card
System Control
Processor
Ethernet Line Card
MAC
Linecard Control
Processor
Packet
Processing
VSC8584
MAC
Ethernet Port
Ethernet Line Card
Linecard Control
Processor
Ethernet Port
VSC8584
Fabric
Adapter
Fabric
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability
whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction
with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone
and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability
of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer.
Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in
this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.

VSC8584XKS-14相似产品对比

VSC8584XKS-14 VSC8584XKS-11
描述 4P Q/SGMII CU/FI 3E, 256, 4NS IN 4P Q/SGMII CU/FI 3E, 256, 4NS CO
本人初学嵌入式,求一些简单的程序
比如控制数码管、键盘、LCD的 希望能给我发一下 jimmy111529@sohu.com...
lynker 嵌入式系统
各位高人 请问谁有详细点的基于cpld信号发生器的设计资料....
各位大侠们 有CPLD 信号发生器的设计的资料的请帮帮忙~~~谢谢...
wangsheng11 FPGA/CPLD
请教此处窗口比较器的作用
这个地方使用窗口比较和使用单比较器的区别是什么? 416051 https://m.eeworld.com.cn/ic_article/263/1774.html ...
littleshrimp 模拟电子
74hc595级联时如何写入数据
用单个595,编写程序成功。可是两个级联不知如何写入数据使LED灯逐个点亮。请指教,一片595的代码如下: #include <reg52.h> //51芯片管脚定义头文件#include <intrins.h> //内部包 ......
esobao 51单片机
ATMLH118 2FC D 可以替换AT24C512吗?
网上找不到ATMLH118 2FC D 的资料啊...
wanghlady 单片机
FPGA课件
本课件下载与61eda 36383...
zhangkai0215 FPGA/CPLD

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 362  1772  664  2536  1048  59  37  22  31  47 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved