UA5M20MC Datasheet
CENTELLAX
5 - 20GHz MMIC Amplifier with Integrated Bias
Application
The UA5M20MC MMIC Amplifier with Integrated
Bias is designed for digital radio, spread spectrum,
electronic warfare, and broadband communication
systems. It can be used as a LO or mixer isolation
amplifier, a transmit amplifier in a radio system, or as
a general isolation and gain block amplifier.
Device Highlights
•
Excellent performance 5-18GHz:
•
High, flat gain (15 ± 0.5dB)
•
Good return loss (15dB)
•
17.5dBm P
-1dB
, 20dBm P
sat
•
Mixed-signal 3.3V operation:
•
Similar small-signal performance
•
Good power (16.5dBm P
sat
)
•
Quick and easy to use:
•
Self-biasing (5V or 3.3V supply)
•
Integrated blocking capacitors
•
Very high isolation (-36dB)
•
100% DC, RF, and visually tested
•
Size: 920x920um (36.2x36.2mil)
Description
The UA5M20MC is a two-stage PHEMT high gain
amplifier designed to be insensitive to process or
temperature changes. Its high isolation make it ideal
for applications requiring both gain and isolation.
The device can be operated at 5V 135mA, or 3.3V
108mA for integration with mixed-signal circuitry.
Features
The UA5M20MC is typically self-biased for low-cost
Class-A operation, requiring only a single 5V supply;
both drain and both gate pads are available for
higher-efficiency operation. The device is AC cou-
pled with integrated blocking capacitors.
Key Specifications
Specifications pertain to wafer measurements with RF probes
and DC bias cards @ 25°C
Vdd1=Vdd2=5.0V, Vg1=Vg2=N/C, Idd1=65mA, Idd2=90mA, Zo=50Ω
5 - 18GHz
Parameter
S21 (dB)
Flatness (±dB)
S11 (dB)
S22 (dB)
S12 (dB)
P
-1dB
(dBm)
P
sat
(dBm)
NF (dB)
4.5 - 20GHz
Max
Min
12.5
0.8
-13
-11.5
-32
Description
Small Signal Gain
Gain Flatness
Input Match
Output Match
Reverse Isolation
1dB Compressed Output Power
Saturated Output Power
Noise Figure
Min
14
Typ
15
0.5
-15
-17
-36
17.5
20
7
Typ
14.5
1.0
-15
-17
-36
17
20
7.5
Max
2.0
-13
-12
-32
16
19
18.5
CENTELLAX
• Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. Copyright © 2001-2007 Centellax, Inc. Printed in USA. 27 Jun 2007.
UA5M20MC S21
20
8
7
15
6
5
S21 (dB)
10
NF (dB)
4
3
5
5V, 135mA
3.3V, 108mA
UA5M20MC Noise Figure
2
1
0
4.5
6.5
8.5
10.5
12.5
14.5
16.5
18.5
20.5
4.5
6.5
8.5
10.5
12.5
14.5
16.5
18.5
20.5
Frequency (GHz)
Frequency (GHz)
5V, 135mA
3.3V, 108mA
0
Typical IC performance measured on-wafer
UA5M20MC S11, S22
0
3.3V, 108mA S11
5V, 135mA S11
3.3V, 108mA S22
5V, 135mA S22
Typical IC performance with package de-embedded
UA5M20MC S12
0
5V, 135mA
3.3V, 108mA
-5
-10
S11, S22 (dB)
-10
S12 (dB)
4.5
6.5
8.5
10.5
12.5
14.5
16.5
18.5
20.5
-20
-15
-30
-20
-40
-25
-30
Frequency (GHz)
-50
4.5
6.5
8.5
10.5
12.5
14.5
16.5
18.5
20.5
Frequency (GHz)
Typical IC performance measured on-wafer
UA5M20MC Output Power
22
21
20
120
Output Power (dB)
Group Delay (ps)
19
18
17
16
15
14
13
12
4.5
6.5
8.5
10.5
12.5
14.5
16.5
18.5
20.5
Frequency (GHz)
5V, 135mA Psat
3.3V, 108mA Psat
5V, 135mA P-1
3.3V, 108mA P-1
0
20
100
80
60
40
160
140
Typical IC performance measured on-wafer
UA5M20MC Group Delay
5V, 135mA
3.3V, 108mA
4.5
6.5
8.5
10.5
12.5
14.5
16.5
18.5
20.5
Frequency (GHz)
Typical IC performance measured on-wafer
Typical IC performance measured on-wafer
Typical measurement data is available upon request. Email support@centellax.com for more information.
CENTELLAX
• Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Supplemental Specifications
Parameter
Vdd1
Idd1
Vdd2
Idd2
Vgg1
Vgg2
P
in
P
dc
T
ch
Θ
ch
Description
Drain
Drain
Drain
Drain
Bias
Bias
Bias
Bias
Voltage FET1
Current FET1
Voltage FET2
Current FET2
Min
3V
—
3V
—
-4V
-4V
Typ
5V
65mA
5V
90mA
N/C
N/C
Max
6V
90mA
6V
110mA
+1V
+1V
12dBm
0.675W
150°C
60°C/W
Gain Control
Some gain control is available
when operating the amplifier in
the linear gain region. Negative
voltage applied to Vgg1 and Vgg2
will reduce the amplifier gain.
Additionally, Vdd1 and Vdd2 can
also be used for linear low-fre-
quency amplitude modulation.
Gate Bias Voltage FET1
Gate Bias Voltage FET2
Input Power (CW)
Power Dissipation
Channel Temperature
Thermal Resistance (T
case
=85°C)
Matching
The UA5M20MC has been
designed with input and output
impedances that best match a
50ohm system, and require no
external matching networks.
Best performance will be
obtained by using multiple short
bondwires, or by using ribbon or
mesh bondwires.
DC Bias
The UA5M20MC is typically biased by
applying +5V to the two drain pads
(Vdd1, Vdd2); the gates (Vgg1, Vgg2)
will self-bias.
All four bias lines are available on-
chip; both drains and both gates can
be biased to different potentials.
Grounded bond wires are not
required, as the backside of the chip is
both an RF and DC ground.
Negative potentials applied to the
gates will reduce the drain current
in that stage. This will increase
the amplifier’s efficiency by mov-
ing its operation closer to Class
AB or B.
The UA5M20MC can also be
biased with +3.3V drain voltage.
This yields good performance
with the same supply used for
mixed-signal circuitry or micro-
processors.
DC Blocks
The amplifier is internally AC cou-
pled to the RF input and output
pads. DC blocking capacitors are
not required for isolating bias volt-
ages from external circuitry.
CENTELLAX
• Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
UA5M20MC Datasheet
CENTELLAX
Chip size: 920x920um (36.2x36.2mil)
Chip size tolerance: ±5um (0.2mil)
Chip thickness: 100 ±10um (4 ±0.4mil)
Pad dimensions: 80x80um (3.1x3.1mil)
Die size, pad locations, and pad descriptions
Applications Support
Alternate assembly diagrams and other additional
application support are available upon request.
Visit the Centellax website for large printable
assembly diagrams and application notes:
http://www.centellax.com/products/microwave/mmi
cs/UA5M20MC.shtml.
Pick-up and Chip Handling:
This MMIC has exposed air bridges on the top sur-
face.
Do not pick up chip with vacuum on the
die center;
handle from edges or with a custom
collet.
Thermal Heat Sinking:
To avoid damage and for optimum performance,
you must observe the maximum channel tempera-
ture and ensure adequate heat sinking.
Single supply (self-biased) assembly diagram
ESD Handling and Bonding:
This MMIC is ESD sensitive;
preventive meas-
ures should be taken during handling, die attach,
and bonding.
Epoxy die attach is recommended.
Please visit
our website for more handling, die attach and bond-
ing information: http://www.centellax.com/.
Recommended Components
>100pF 25x25mil Bypass Capacitor:
Presidio SL2525X7R101K16VH
Dual supply (externally-biased) assembly diagram
CENTELLAX
• Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. Copyright © 2001-2007 Centellax, Inc. Printed in USA. 27 Jun 2007.
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