74ALVC16835A
Rev. 7 — 19 January 2018
18-bit registered driver; 3-state
Product data sheet
1
General description
The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low
output enable (OE), active low latch enable (LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held
at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is
stored in the latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the
high impedance OFF–state. Operation of the OE input does not affect the state of the
latch/flip-flop.
To ensure the high-impedance state during power up or power down, OE should be tied
to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the
current-sinking capability of the driver.
2
Features and benefits
•
•
•
•
•
•
•
•
•
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
Output drive capability 50 Ω transmission lines at 85°C
Input diodes to accommodate strong drivers
Complies with JEDEC standards:
–
JESD8-5 (2.3 V to 2.7 V)
–
JESD8B/JESD36 (2.7 V to 3.6 V)
•
ESD protection:
–
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
–
CDM JESD22-C101E exceeds 1000 V
3
Ordering information
Package
Temperature range Name
Description
Version
SOT364-1
−40 °C to + 85 °C
TSSOP56 plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
Table 1. Ordering information
Type number
74ALVC16835ADGG
Nexperia
74ALVC16835A
18-bit registered driver; 3-state
4
Functional diagram
27
OE
30
CP
28
LE
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
EN1
2C3
G3
G2
3D
1
1
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
OE
CP
LE
A1
D
LE
CP
Y1
to the 17 other channels
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
aaa-027574
aaa-027575
Figure 1. Logic diagram
V
CC
Figure 2. Logic symbol (IEEE/IEC)
A1
002aac725
Figure 3. Typical input (data or control)
74ALVC16835A
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 7 — 19 January 2018
2 / 15
Nexperia
74ALVC16835A
18-bit registered driver; 3-state
5
Pinning information
5.1 Pinning
74ALVC16835A
n.c.
n.c.
Y1
GND
Y2
Y3
V
CC
Y4
Y5
1
2
3
4
5
6
7
8
9
56 GND
55 n.c.
54 A1
53 GND
52 A2
51 A3
50 V
CC
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 V
CC
34 A16
33 A17
32 GND
31 A18
30 CP
29 GND
aaa-028080
Y6 10
GND 11
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
GND 18
Y13 19
Y14 20
Y15 21
V
CC
22
Y16 23
Y17 24
GND 25
Y18 26
OE 27
LE 28
Figure 4. Pin configuration SOT364-1 (TSSOP56)
74ALVC16835A
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 7 — 19 January 2018
3 / 15
Nexperia
74ALVC16835A
5.2 Pin description
18-bit registered driver; 3-state
Table 2. Pin description
Symbol
A1, A2, A3, A4, A5, A6,
A7, A8, A9, A10, A11, A12,
A13, A14, A15, A16, A17, A18
Y1, Y2, Y3, Y4, Y5, Y6,
Y7, Y8, Y9, Y10, Y11, Y12,
Y13, Y14, Y15, Y16, Y17, Y18
n.c.
LE
OE
CP
GND
V
CC
Pin
54, 52, 51, 49, 48, 47,
45, 44, 43, 42, 41, 40,
38, 37, 36, 34, 33, 31
3, 5, 6, 8, 9, 10,
12, 13, 14, 15, 16, 17,
19, 20, 21, 23, 24, 26
1, 2, 55
28
27
30
4, 11, 18, 25, 32, 39, 46, 53, 56
7, 22, 35, 50
Description
data inputs
data outputs
not connected
latch enable input
output enable input (active LOW)
clock input
ground (0 V)
supply voltage
6
Functional description
[1]
Table 3. Function table
Input
OE
H
L
L
L
L
L
L
Output
LE
X
H
H
L
L
L
L
CP
X
X
X
↑
↑
H
L
An
X
L
H
L
H
X
X
Yn
Z
L
H
L
H
Yn
Yn
[2]
[3]
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
[2] Yn = Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low.
[3] Yn = Output level before the indicated steady-state input conditions were established.
74ALVC16835A
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 7 — 19 January 2018
4 / 15
Nexperia
74ALVC16835A
18-bit registered driver; 3-state
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
[2]
Conditions
For control pins
For data inputs
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
[1]
[1]
[1]
Min
-0.5
-0.5
-0.5
-0.5
-50
-
-
-
-100
-65
-
Max
+4.6
+4.6
Unit
V
V
V
CC
+ 0.5 V
V
CC
+ 0.5 V
-
±50
±50
+100
-
+150
600
mA
mA
mA
mA
mA
°C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP56 package: P
tot
derates linearly with 8 mW/K above 55 °C.
8
Recommended operating conditions
Parameter
supply voltage
Conditions
2.5 V range for maximum speed performance
at 30 pF output load
3.3 V range for maximum speed performance
at 50 pF output load
for low-voltage applications
Min
2.3
3.0
1.2
0
0
operating in free-air
V
CC
= 2.3 V to 3.0 V
V
CC
= 3.0 V to 3.6 V
−40
0
0
Typ
-
-
-
-
-
-
-
-
Max
2.7
3.6
3.6
V
CC
V
CC
+85
20
10
Unit
V
V
V
V
V
°C
ns/V
ns/V
Table 5. Recommended operating conditions
Symbol
V
CC
V
I
V
O
T
amb
Δt/ΔV
input voltage
output voltage
ambient temperature
input transition
rise and fall rate
74ALVC16835A
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 7 — 19 January 2018
5 / 15
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