TN2425TG
Low Threshold Dual N-Channel Enhancement-Mode
Vertical DMOS FET
Features
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Dual N-channel device
Low threshold – 2.0V max.
High input impedance
Low input capacitance – 200pF
Fast switching speeds
Low caps ON resistance
Free from secondary breakdown
Low input and output leakage
General Description
The Supertex TN2425TG is a dual low threshold
enhancement mode (normally off) transistor utilizing
a vertical DMOS structure and Supertex’s well proven
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities
of bipolar transistors, with the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Applications
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Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Medical ultrasound pulsers
Analog switches
General purpose line drivers
Telecom switches
Ordering Information
Device
TN2425TG
Package Option
8-Lead SOIC (Narrow Body)
TN2425TG
BV
DSS
/BV
DGS
250V
R
DS(ON)
(max)
3.5Ω
V
GS(th)
(max)
2.0V
I
D(ON)
(min)
1.8A
Absolute Maximum Ratings
Parameter
Drain to source voltage
Drain to gate voltage
Gate to source voltage
Thermal resistance,
Junction to drain lead
Operating and storage temperature
Soldering temperature
1
Value
BV
DSS
BV
DGS
±20V
50°C/W
Pin Configuration
S1
1
8
D1
G1
2
7
D1
S2
-55°C to +150°C
+300°C
3
6
D2
G2
4
5
D2
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
Note 1.
Distance of 1.6mm from case for 10 seconds.
8-Lead SOIC
(top view)
TN2425TG
Electrical Characteristics
(each device, T =25°C unless otherwise specified)
J
Symbol
Parameter
Min
Typ
Max
Units
Conditions
BV
DSS
V
GS(th)
ΔV
Match
ΔV
GS(th)
I
GSS
I
DSS
Drain-to-source breakdown voltage
Gate threshold voltage
Change in V
GS(th)
with temperature
V
GS(th)
change with temperature
Gate body leakage current
Zero gate voltage drain current
250
0.6
-
-
-
-
-
1.5
1.8
-
-
-
-
300
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
115
30
10
-
-
-
5
10
25
5
-
300
-
2.0
25
-5.0
100
10
1.0
-
-
5.0
3.5
20
1.4
-
5
5
200
100
40
25
25
25
15
25
35
15
1.8
-
V
V
mV
mV/
O
C
nA
µA
mA
A
Ω
%
%/
O
C
mmho
%
%
pF
V
GS
= 0V, I
D
= 250µA
V
GS
= V
DS
, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA,
T
A
= 10
O
C - 80
O
C
V
GS
= V
DS
, I
D
= 1mA
V
GS
= ±20V, V
DS
= 0V
V
DS
= Max rating, V
GS
= 0V
V
DS
= 0.8 Max Rating,
V
GS
= 0V, T
A
= 125
O
C
V
GS
= 6.0V, V
DS
= 25V
V
GS
= 10V, V
DS
= 25V
V
GS
= 4.5V, I
D
= 300mA
V
GS
= 10V, I
D
= 400mA
V
GS
= 10V, I
D
= 400mA
V
GS
= 10V, I
D
= 400mA
V
DS
= 15V, I
D
= 400mA
V
DS
= 15V, I
D
= 50mA
V
GS
= 15V, I
D
= 1.50A
V
GS
= 0V, V
DS
= 25V, f = 1MHz
I
D(ON)
R
DS(ON)
R
MATCH
ΔR
DS(ON)
G
FS
G
FSMATCH
C
ISS
C
OSS
C
RSS
C
ISSMATCH
C
OSSMATCH
C
RSSMATCH
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
ON-state drain current
Static drain-to-source ON-state
resistance
Channel to channel R
DS(ON)
matching
Change in R
DS(ON)
with temperature
Forward transconductance
Channel to channel G
FS
matching
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Channel to channel C
ISS
matching
Channel to channel C
OSS
matching
Channel to channel C
RSS
matching
Turn-ON delay time
Rise time
Turn-OFF delay time
Fall time
Diode forward voltage drop
Reverse recovery time
%
V
GS
= 0V, V
DS
= 25V, f = 1MHz
ns
V
DD
= 25V, I
D
= 500mA,
R
GEN
= 25Ω
V
GS
= 0V, I
SD
= 500mA
V
GS
= 0V, I
SD
= 500mA
V
ns
Notes:
1.All D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2.All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
V
DD
R
L
OUTP
90%
INPUT
0V
10%
t
(ON)
PULSE
GENERATOR
t
(OFF)
t
r
t
d(OFF)
t
F
R
GEN
t
d(ON)
V
DD
10%
10%
INPUT
D.U.T.
OUTPUT
0V
90%
90%
2
TN2425TG
Typical Performance Curves
Output Characteristics
5
3.0
Saturation Characteristics
4
2.5
V
GS
= 10V
8V
6V
5V
I
D
(Amperes)
I
D
(Amperes)
V
GS
= 10V
8V
6V
5V
2.0
4V
1.5
3
2
4V
1.0
3V
1
3V
2.5V
0
0
10
20
30
40
50
0.5
2.5V
0.0
0
2
4
6
8
10
V
DS
(Volts)
Transconductance vs. Drain Current
1.0
T
A
=-55
O
C
0.8
V
DS
=15V
1.2
BV @ 250A
V
DS
(Volts)
BV
DSS
Variation with Temperature
BV
DSS
(Normalized)
1.1
G
FS
(siemens)
T
A
=25
O
C
0.6
T
A
=125
O
C
0.4
1.0
0.9
0.2
0.0
0.0
0.5
1.0
1.5
2.0
0.8
-50
0
50
100
150
I
D
(Amperes)
On Resistance vs. Drain Current
10
3.0
T
J
(
O
C)
Transfer Characteristics
T
A
= 25
O
C
8
V
GS
= 4.5V
2.5
R
DS(ON)
(ohms)
I
D
(Amperes)
2.0
T
A
= -55
O
C
1.5
T
A
= 125
O
C
6
4
V
GS
= 10V
2
1.0
0.5
0
V
DS
= 25V
0
1
2
3
4
5
0.0
0
2
4
6
8
10
I
D
(Amperes)
3
V
GS
(Volts)
TN2425TG
8-Lead SOIC (Narrow Body) Package Outline (TG)
4.90 ± 0.10
8
6.00 ± 0.20
3.90 ± 0.10
Note 2
1
Top View
0.17 - 0.25
1.75 MAX
1.25 MIN
5° - 15°
(4 PLCS)
45°
0.25 - 0.50
Note 2
0° - 8°
0.10 - 0.25
1.27BSC
0.40 - 1.27
0.31 - 0.51
Side View
Notes:
1. All dimensions in millimeters. Angles in degrees.
2. If the corner is not chamfered, then a Pin 1 identifier
must be located within the area indicated.
End View
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to
http://www.supertex.com/packaging.html.)
Doc.# DSFP-TN2425TG
NR111506
5
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