Data Sheet
Rev.1.0
20.06.2011
2048MB DDR3
– SDRAM ECC
XR-DIMM
TM
240 Pin ECC XR-DIMM
TM
SGV02G72A1BC1SA-xxRT
2GB in FBGA Technology
RoHS compliant
Features:
eXtreme Rugged 240-pin 72-bit DDR3 Small Outline
Double Data Rate synchronous DRAM Module
67.5 mm x 38 mm module that stacks 7.36mm above
CPU board
Samtec BSH-120-01-X-D-A connector
Socket ANSI/VITA 47-2005 shock and vibration compliant
Module organization: single rank 256M x 72
V
DD
= 1.5V ±0.075V, V
DDQ
1.5V ±0.075V
1.5V I/O ( SSTL_15 compatible)
Fly-by-bus with termination for C/A & CLK bus
On-board I2C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
Compatible to XR-DIMM™ 2.0 specification of SFF-SIG
(see
www.sff-sig.org)
The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR3 - SDRAM component Samsung K4B2G0846C
256Mx8 DDR3 SDRAM in PG-TFBGA-78 package
8-bit prefetch architecture
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
On-Die-Termination (ODT) and Dynamic ODT for
improved signal integrity.
Refresh, Self Refresh and Power Down Modes.
Options:
Data Rate / Latency
DDR3 1066 MT/s CL7
DDR3 1333 MT/s CL9
Module density
2048MB with 9 dies and 1 rank
Standard Grade
Grade W
(T
A
)
(T
C
)
(T
A
)
(T
C
)
0°C to 70°C
0°C to 85°C
-40°C to 85°C
-40°C to 95°C
Marking
-BB
-CC
Environmental Requirements:
Operating temperature (ambient)
Standard Grade
0°C to 70°C
Grade W
-40°C to 85°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Figure:
mechanical dimensions
1
1
if no tolerances specified ± 0.15mm
Page 1
of 16
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Data Sheet
Rev.1.0
20.06.2011
This Swissbit module is a highly ruggedized 240-pin 72bit DDR3 SDRAM ECC Small Outline module which is
organized as 256Mx72 high speed CMOS memory arrays. Enhanced ruggedness is obtained through the use of
a high-performance, 240-pin socket connector system and the use of standoffs with screw attachment firmly
holding the CPU and memory module together. The module uses internally configured octal-bank DDR3 SDRAM
devices. The module uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM
modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module
is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence. The burst length is either four or eight locations. An auto precharge function can be
enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM
devices have a multibank architecture which allows a concurrent operation that is providing a high effective
bandwidth. A self refresh mode is provided and a power-saving ―power-down‖ mode. All inputs and all full drive-
strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
2
using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the XR-DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
256M x 72bit
DDR3 SDRAMs used
9 x 256M x 8bit (2048Mbit)
Row
Addr.
15
Device Bank
Addr.
BA0, BA1, BA2
Column
Refresh
Addr.
10
8k
Module
Bank Select
S0#
Module Dimensions
in mm
67.5mm (long) x 38mm(high) x 7.36mm(standoff from CPU board)
Timing Parameters
Part Number
SGV02G72A1BC1SA-BB[W]RT
SGV02G72A1BC1SA-CC[W]RT
Module Density
2048 MB
2048 MB
Transfer Rate
8.5 GB/s
10.6 GB/s
Clock Cycle/Data bit rate
1.87ns/1066MT/s
1.5ns/1333MT/s
Latency
7-7-7
9-9-9
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 16
Data Sheet
Rev.1.0
20.06.2011
Pin Name
Symbol
Type
Polarity
Function
During a Bank Activate command cycle, address input defines the row address (RA0–
RA14).
During a Read or Write command cycle, address input defines the column address. In
addition to the column address, AP is used to invoke autoprecharge operation at the end
of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1,
BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a
Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the
state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to define which
bank to precharge.
A12(BC_n) is sampled during READ and WRITE commands to determine if burst chop
(on-the-fly) will be performed (HIGH, no burst chop; LOW, burst chopped).
Selects which SDRAM bank of eight is activated.
CK_t and CK_c are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are
sampled on the crossing of positive edge of CK_t and negative edge of CK_c. Output
(read) data is referenced to the crossing of CK_t and CK_c (Both directions of crossing).
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode.
DM is an input mask signal for write data. Input data is masked when DM is sampled
High coincident with that input data during a write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading.
Data and Check Bit Input/Output pins.
Data strobe for input and output data. For raw cards using x16 organized DRAMs, Pins
DQ0–DQ7 are associated with the LDQS_t and LDQS_c pins and Pins DQ8–DQ15 are
associated with UDQS_t and UDQS_c pins.
When high, termination resistance is enabled for all DQ, DQS_t, DQS_c and DM pins,
assuming this function is enabled on the DRAM.
RAS_n, CAS_n, and WE_n (along with S_n) define the command being entered.
The RESET_n pin is connected to the RESET_n pin on each DRAM. When low, all
DRAMs are set to a known state.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. This signal provides for external rank selection
on systems with multiple ranks.
Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD and VDDQ
pins are tied to VDD/VDDQ planes on these modules.
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity.
For the DDR3 XR-DIMM designs, VDDQ shares the same power plane as VDD pins.
Termination voltage for C/A & Control bus, by default at VDD/2
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power
plane. EEPROM supply is operable from 3.0V to 3.6V.
Reference voltage for I/O inputs, by default at VDD/2
Reference voltage for command/address/control inputs, by default at VDD/2
—
—
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An
external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup
on the system board.
This signal is used to clock data into and out of the SPD EEPROM. An external resistor
may be connected from the SCL bus time to VDDSPD to act as a pullup on the system
board.
This signal indicates that a thermal event has been detected in the thermal sensing
device. The system should guarantee the electrical level requirement is met for the
EVENT_n pin on the TS/SPD part.
Used by memory bus analysis tools (unused (NC) on memory module)
Not connected
A0–A14
IN
—
BA0–BA2
CK0_t–CK1_t
CK0_c–CK1_c
CKE0
IN
IN
—
Differential
crossing
Active High
IN
DM0–DM8
DQ0–DQ63,
CB0–CB7
DQS0_t–DQS8_t
DQS0_c–DQS8_c
ODT0
RAS_n, CAS_n,
WE_n
RESET_n
IN
Active High
I/0
I/O
IN
IN
IN
—
Differential
crossing
Active High
Active Low
Active Low
S0_n
IN
Active Low
VDD, VSS
VDDQ
VTT
VDDSPD
VREFDQ
VREFCA
SA0–SA2
SDA
Supply
Supply
Supply
Supply
Supply
Supply
IN
I/O
SCL
IN
Output
(Open Drain)
—
EVENT_n
NC(TEST)
NC
Active Low
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 16
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