288 Pin DDR4 1.2V 2400 ECC UDIMM
4GB Based on 512Mx8
AQD-D4U4GE24-SG
Description
DDR4 1.2V ECC Unbuffered DIMM is high-speed, low
power memory module that use 512Mx8bits DDR4
SDRAM in FBGA package and a 4096 bits serial
EEPROM on a 288-pin printed circuit board. DDR4 1.2V
Unbuffered DIMM is a Dual In-Line Memory Module and
is intended for mounting into 288-pin edge connector
sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
CKE0, CKE1
Register clock enable lines input
Register on-die termination control lines
ODT0, ODT1
input
ACT_n
DQ0–DQ63
CB0–CB7
DQS0_t–
DQS17_t
DQS0_c–
DQS17_c
CK0_t, CK1_t
differential pair)
Register clocks input (negative line of
CK0_c, CK1_c
differential pair)
I2C serial bus clock for SPD/TS and
SCL
register
I2C serial bus data line for SPD/TS and
SDA
register
Register input for activate input
DIMM memory data bus
DIMM ECC check bits
Data Buffer data strobes (positive line
of differential pair)
Data Buffer data strobes (negative line
of differential pair)
Register clock input (positive line of
Pin Identification
Symbol
A0–A17
BA0, BA1
BG0, BG1
RAS_n2
CAS_n3
WE_n4
CS0_n, CS1_n,
DIMM Rank Select Lines input
CS2_n, CS3_n
Function
Register address input
Register bank select input
Register bank group select input
Register row address strobe input
Register column address strobe input
Register write enable input
Features
RoHS compliant products
JEDEC standard 1.2V (1.14V to 1.26V) Power supply
VDDQ=1.2V (1.14V to 1.26V)
Clock Freq: 1200MHZ for 2400Mb/s/Pin
16 Banks (4 Bank Groups)
Programmable CAS Latency: 10, 11, 12, 13, 14,15,16,
17,18
Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
Programmable /CAS Write Latency (CWL)
= 12,16 (DDR4-2400)
8 bit pre-fetch
Burst Length: 4, 8
Bi-directional Differential Data-Strobe
On Die Termination with ODT pin
Serial presence detect with EEPROM
Asynchronous reset
PCB: 30µ gold finger
Advantech
2
288 Pin DDR4 1.2V 2400 ECC UDIMM
4GB Based on 512Mx8
AQD-D4U4GE24-SG
I2C slave address select for SPD/TS
SA0–SA2
and register
PAR
VDD
VPP
VREFCA
supply
VSS
VDDSPD
ALERT_n
RESET_n
State
SPD signals a thermal event has
EVENT_n
occurred
VTT
RFU
NC
SDRAM I/O termination supply
Reserved for future use
No Connection
Power supply return (ground)
Serial SPD/TS positive power supply
Register ALERT_n output
Set Register and SDRAMs to a Known
Register parity input
SDRAM core power supply
SDRAM activating power supply
SDRAM command/address reference
Advantech
3
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