AS4C128M8D3LA-12BIN
AS4C128M8D3LA-12BCN
Features
•
JEDEC Standard Compliant
•
Power supplies: V
DD
& V
DDQ
= +1.35V
•
Backward compatible to V
DD
& V
DDQ
= 1.5V ±0.075V
•
Operating
temperature:
Commercial: 0°C to 95°C
(TC)
Industrial :-40°C to 95°C
(TC)
•
Supports JEDEC clock jitter specification
•
Fully synchronous operation
•
Fast clock rate: 800MHz
•
Differential Clock, CK & CK#
•
Bidirectional differential data strobe
- DQS & DQS#
•
8 internal banks for concurrent operation
•
8n-bit prefetch architecture
•
Pipelined internal architecture
•
Precharge & active power down
•
Programmable Mode & Extended Mode registers
•
Additive Latency (AL): 0, CL-1, CL-2
•
Programmable Burst lengths: 4, 8
•
Burst type: Sequential / Interleave
•
Output Driver Impedance Control
•
8192 refresh cycles / 64ms
- Average refresh period
7.8µs @ -40°C
≦
TC
≦
+85°C
3.9µs @ +85°C
＜TC
≦
+95°C
•
Write Leveling
•
ZQ Calibration
•
Dynamic ODT (Rtt_Nom & Rtt_WR)
•
RoHS compliant
•
Auto Refresh and Self Refresh
•
78-ball 8 x 10.5 x 1.0mm FBGA package
- Pb and Halogen Free
Overview
The 1Gb Double-Data-Rate-3 (DDR3L) DRAMs is
double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank
DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/Os x 8
bank devices. These synchronous devices achieve
high speed double-data-rate transfer rates of up to
1600 Mb/sec/pin for general applications. The chip is
designed to comply with all key DDR3L DRAM key
features and all of the control and address inputs are
synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential
clocks (CK rising and CK# falling). All I/Os are synchronized
with differential DQS pair in a source synchronous
fashion.
These devices operate with a single 1.35V -0.067V
/+0.1V power supply and are available in BGA packages.
Table 1. Ordering Information
Product part No
AS4C128M8D3LA-12BCN
AS4C128M8D3LA-12BIN
Org
128M
x
8
128M
x
8
Temperature
Commercial 0°C to 95°C
Industrial -40°C
to 95°C
Max Clock (MHz)
800
800
Package
78-ball
FBGA
78-ball
FBGA
Table 2. Speed Grade Information
Speed Grade
DDR3L-1600
Clock Frequency
800 MHz
CAS Latency
11
t
RCD
(ns)
13.75
t
RP
(ns)
13.75
Confidential
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Rev.1.0 Sep. 2016
AS4C128M8D3LA-12BIN
AS4C128M8D3LA-12BCN
Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the
commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die
termination, and some other events are not captured in full detail.
Power
applied
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
SR
SR E
X
Self
Refresh
from any
RESET
state
ZQCL
MRS
ZQ
Calibration
ZQCL,ZQCS
Idle
REF
Refreshing
E
PD X
PD
ACT
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Active
Power
Down
PD
X
PD
E
Activating
Precharge
Power
Down
Bank
Activating
RE
AD
W
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
WR
WRITE
Writing
ITE
Write = WR, WRS4, WRS8
A
TE
RI
READ
WRITE
READ
AD
RE
A
Reading
WRITE A
READ A
EA
RIT
W
RE
AD
A
PRE, PREA
Writing
PR
E
,P
RE
A
P
E,
PR
A
RE
Reading
Automatic Sequence
Command Sequence
Precharging
Confidential
- 5/83 -
Rev.1.0 Sep. 2016
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