Intel
®
Cyclone
®
10 LP Device
Overview
C10LP51001
2017.05.08
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Contents
Contents
Cyclone
®
10 LP Device Overview........................................................................................ 3
Summary of Cyclone 10 LP Features............................................................................... 4
Cyclone 10 LP Available Options..................................................................................... 5
Cyclone 10 LP Maximum Resources ............................................................................... 6
Cyclone 10 LP Package Plan ..........................................................................................6
Cyclone 10 LP I/O Vertical Migration............................................................................... 7
Logic Elements and Logic Array Blocks............................................................................ 7
Embedded Multipliers................................................................................................... 8
Embedded Memory Blocks.............................................................................................8
Clocking and PLL..........................................................................................................9
FPGA General Purpose I/O.............................................................................................9
Configuration...............................................................................................................9
Power Management.................................................................................................... 10
Document Revision History for Cyclone 10 LP Device Overview......................................... 10
Intel
®
Cyclone
®
10 LP Device Overview
2
Cyclone
®
10 LP Device Overview
Cyclone
®
10 LP Device Overview
The Intel
®
Cyclone
®
10 LP FPGAs are optimized for low cost and low static power,
making them ideal for high-volume and cost-sensitive applications.
Cyclone 10 LP devices provide a high density sea of programmable gates, on-board
resources, and general purpose I/Os. These resources satisfies the requirements of
I/O expansion and chip-to-chip interfacing. The Cyclone 10 LP architecture suits smart
and connected end applications across many market segments:
•
•
•
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Industrial and automotive
Broadcast, wireline, and wireless
Compute and storage
Government, military, and aerospace
Medical, consumer, and smart energy
The free but powerful Quartus
®
Prime Lite Edition software suite of design tools meets
the requirements of several classes of users:
•
•
•
Existing FPGA designers
Embedded designers using the FPGA with Nios
®
II processor
Students and hobbyists who are new to FPGA
Advanced users who require access to the full IP Base Suite can subscribe to the
Quartus Prime Standard Edition or purchase the license separately.
Related Links
•
Software Development Tools, Nios II Processor
Provides more information about the Nios II 32-bit soft IP processor and
Embedded Design Suite (EDS).
Quartus Prime IP Base Suite
Quartus Prime Editions
•
•
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
Cyclone
®
10 LP Device Overview
Summary of Cyclone 10 LP Features
Table 1.
Summary of Features for Cyclone 10 LP Devices
Feature
Technology
•
•
•
•
Description
Low-cost, low-power FPGA fabric
1.0 V and 1.2 V core voltage options
Available in commercial, industrial, and automotive temperature grades
Several package types and footprints:
— FineLine BGA (FBGA)
— Enhanced Thin Quad Flat Pack (EQFP)
— Ultra FineLine BGA (UBGA)
— Micro FineLine BGA (MBGA)
Multiple device densities with pin migration capability
RoHS6 compliance
Logic elements (LEs)—four-input look-up table (LUT) and register
Abundant routing/metal interconnect between all LEs
M9K—9-kilobits (Kb) of embedded SRAM memory blocks, cascadable
Configurable as RAM (single-port, simple dual port, or true dual port), FIFO buffers, or ROM
One 18 × 18 or two 9 × 9 multiplier modes, cascadable
Complete suite of DSP IPs for algorithmic acceleration
Global clocks that drive throughout entire device, feeding all device quadrants
Up to 15 dedicated clock pins that can drive up to 20 global clocks
Up to four general purpose PLLs
Provides robust clock management and synthesis
Multiple I/O standards support
Programmable I/O features
True LVDS and emulated LVDS transmitters and receivers
On-chip termination (OCT)
Packaging
•
•
Core architecture
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•
•
•
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•
•
•
•
•
•
•
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Internal memory
blocks
Embedded multiplier
blocks
Clock networks
Phase-locked loops
(PLLs)
General-purpose I/Os
(GPIOs)
SEU mitigation
Configuration
SEU detection during configuration and operation
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•
•
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Active serial (AS), passive serial (PS), fast passive parallel (FPP)
JTAG configuration scheme
Configuration data decompression
Remote system upgrade
Intel
®
Cyclone
®
10 LP Device Overview
4
Cyclone
®
10 LP Device Overview
Cyclone 10 LP Available Options
Figure 1.
Sample Ordering Code and Available Options for Cyclone 10 LP Devices—
Preliminary
Package Type
F
E
U
M
L : LP
:
:
:
:
FineLine BGA (FBGA)
Enhanced Thin Quad Flat Pack (EQFP)
Ultra FineLine BGA (UBGA)
Micro FineLine BGA (MBGA)
Operating Temperature
C : Commercial (T
J
= 0°C to 85°C)
I : Industrial (T
J
= -40°C to 100°C)
Extended Industrial (T
J
= -40°C to 125°C)
A : Automotive (T
J
= -40°C to 125°C)
Family Variant
Family Signature
10C : Cyclone 10
10C
L
120
Z
F
780
I
8
GES
Optional Suffix
Member Code
006 :
010 :
016 :
025 :
040 :
055 :
080 :
120 :
6,272 logic elements
10,320 logic elements
15,408 logic elements
24,624 logic elements
39,600 logic elements
55,856 logic elements
81,264 logic elements
119,088 logic elements
Core Voltage
Y : Standard voltage (1.2 V)
Z : Lower core voltage (1.0 V)
FPGA Fabric
Speed Grade
6 (fastest)
7
8
Indicates specific device
options or shipment method
G : RoHS6-compliant packaging
ES : Engineering sample
Package Code
FBGA Package Type
484 : 484 pins
780 : 780 pins
EQFP Package Type
144 : 144 pins
UBGA Package Type
256 : 256 pins
484 : 484 pins
MBGA Package Type
164 : 164 pins
Intel
®
Cyclone
®
10 LP Device Overview
5
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