A4955
Full-Bridge PWM Gate Driver
FEATURES AND BENEFITS
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Standard IN1/IN2 control logic
Overcurrent indication
Adjustable off-time and blank-time
Adjustable current limit
Adjustable gate drive
Synchronous rectification
Internal UVLO
Crossover-current protection
MOSFET VDS protection
Voltage output proportional to load current
A4955K is AEC-Q100 Grade 1 qualified
Commercial temperature grade (A4955G: –40°C to 105°C)
Automotive temperature grade (A4955K: –40°C to 125°C)
DESCRIPTION
Designed for pulse-width-modulated (PWM) control of DC
motors, the A4955 is capable of 50 V operation and provides
gate drive for an all N-channel external MOSFET bridge.
Input terminals are provided for use in controlling the speed and
direction of a DC motor with externally applied PWM control
signals. Internal synchronous rectification control circuitry is
provided to lower power dissipation during PWM operation.
Internal circuit protection includes VDS protection, thermal
shutdown with hysteresis, undervoltage monitoring of VBB,
and crossover-current protection.
The A4955 is supplied in a low-profile 4 × 4 mm, 20-contact
QFN package (suffix “ES”) and a 20-lead eTSSOP (suffix
“LP”), both with exposed thermal pad.
PACKAGES:
20-Pin QFN (suffix “ES”)
with Exposed Thermal Pad
20-Pin eTSSOP (suffix “LP”)
with Exposed Thermal Pad
Not to scale
0.1 µF
TSD
UVLO
CHARGE PUMP
VCP
VBB
0.1 µF
CP2
CP1
VIN
ISET
VREG
RC
STANDBY
SLEEPn
IN1
IN2
OCLn
System
Controller
Control
Logic
GATE
DRIVE
VCP
GHA
GHB
SB
GHA
SA
OCL
Filter
HOLD
×10
+
–
SENSE
GLA
GLB
SA
GLA
optional
AIOUT
R
SENSE
Inrush current limit =
V
REF
/10 * R
SENSE
VREF
÷10
GND
Functional Block Diagram
A4955-DS, Rev. 2
MCO-0000347
November 30, 2017
A4955
Full-Bridge PWM Gate Driver
SPECIFICATIONS
SELECTION GUIDE
Part Number
A4955GESTR-T
A4955GLPTR-T
A4955KLPTR-T
Ambient Temperature Range
–40°C to 105°C
–40°C to 105°C
–40°C to 125°C
Packing
1500 pieces per 7-inch reel
4000 pieces per 13-inch reel
4000 pieces per 13-inch reel
AEC-Q100 Qualified
Notes
ABSOLUTE MAXIMUM RATINGS
Characteristic
Load Supply Voltage
Motor Outputs
SENSE
OCLn
VREF
ISET
AIOUT
Logic Input Voltage Range
Junction Temperature
Storage Temperature Range
Operating Temperature Range
Symbol
V
BB
V
Sx
V
SENSE
V
OCLn
V
REF
V
ISET
V
AIOUT
V
IN
T
J
T
S
T
A
Range G
Range K
SLEEPn, IN1, IN2
V
Sx
– V
SENSE
; V
BB
– V
Sx
t
W
< 500 ns
Notes
Rating
50
–2 to 52
–0.5 to 0.5
–4 to 4
–0.3 to 5.5
–0.3 to 5.5
–0.3 to 5.5
–0.3 to 5.5
–0.3 to 5.5
150
–55 to 150
–40 to 105
–40 to 125
Unit
V
V
V
V
V
V
V
V
V
°C
°C
°C
°C
THERMAL CHARACTERISTICS
(may require derating at maximum conditions; see application information)
Characteristic
ES Package
LP Package
Symbol
R
θJA
4-Layer PCB, 1 in.
2
copper
4-Layer PCB, 1 in.
2
copper
Test Conditions*
Value
37
28
Unit
°C/W
°C/W
*Power dissipation and thermal limits must be observed.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A4955
Full-Bridge PWM Gate Driver
VREF
OCLn
IN1
IN2
RC
GND
AIOUT
15
14
AIOUT
GND
CP1
VBB
CP2
1
2
3
4
5
PAD
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CP1
VBB
CP2
VCP
SA
GHA
SB
GHB
GLA
GLB
20
19
18
17
16
ISET
SLEEPn
SENSE
GLB
GLA
1
2
3
4
5
PAD
OCLn
VREF
IN2
IN1
RC
ISET
SLEEPn
SENSE
13
12
11
SB
GHB
GHA
SA
Package ES, 20-Pin QFN Pinouts
VCP
10
6
8
7
9
Package LP, 20-Pin eTSSOP Pinouts
Terminal List Table
Name
ISET
SLEEPn
SENSE
GLB
GLA
GHB
SB
GHA
SA
VCP
CP2
VBB
CP1
GND
AIOUT
OCLn
VREF
IN2
IN1
RC
PAD
Number
ES Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
–
LP Package
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
–
Terminal to set gate drive current
Sleep input, active low
Sense resistor connection, low-side gate return
Gate driver
Gate driver
Gate driver
High-side bridge reference
Gate driver
High-side bridge reference
Charge pump reservoir cap connection
Charge pump terminal
Supply voltage
Charge pump terminal
Ground
Analog output proportional to V
SENSE
OCP and OVP output flag, open drain
Analog OCP reference input
Digital IN2 input
Digital IN1 input
Terminal to set blank- and off-time
Function
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A4955
Full-Bridge PWM Gate Driver
ELECTRICAL CHARACTERISTICS
: Valid for Temperature Range G version at T
J
= 25°C and
for Temperature Range K
version at T
J
= –40°C to 150°C, V
BB
= 5.5 to 50 V, unless otherwise specified
Characteristics
VBB Supply Current
GATE DRIVE
High-Side Gate Drive Output
Low-Side Gate Drive Output
Gate Drive Pull-Up Current
Gate Drive Pull-Down Current
Dead-Time
Passive Pull-Down Resistance
LOGIC INPUT AND OUTPUT
Logic Output Voltage
Logic Output Leakage
PWM Current Limit Flag Timer
Logic Input Voltage
Logic Input Hysteresis
Logic Input Pull-Down Resistor
VREF Input Current
VREF Input Range
Current Gain
Input Offset, SENSE
Fixed Off-Time
Percent Fast Decay
Blank-Time
Power-Up Delay
AIOUT Gain
Input Offset, AIOUT
Sample-and-Hold Accuracy
Sample-and-Hold Droop Rate
AIOUT Output Impedance
PROTECTION CIRCUITS
UVLO Enable Threshold
UVLO Hysteresis
VDS Threshold
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
[1]
[2]
Symbol
I
BB
I
BB
Test Conditions
SLEEPn = low, Standby Mode
Relative to V
BB
, I
GATE
= 200 µA, V
BB
= 8 to 50 V
Relative to V
BB
, I
GATE
= 200 µA, V
BB
= 5.5 V
I
GATE
= 200 µA, V
BB
= 8 to 50 V
I
GATE
= 200 µA, V
BB
= 5.5 V
R
ISET
= 30 kΩ; V
GH
= V
GL
= 4 V
R
ISET
= 30 kΩ; V
GH
= V
GL
= 4 V
Min.
–
–
6.5
–
6.5
–
21
47
–
30
Typ.
6
–
6.8
5.2
6.8
5.4
30
68
1000
50
0.2
–
500
–
–
–
320
50
<1
–
–
–
30
13
3
50
10
–
15
–
1.00
5.25
300
2
165
30
Max.
10
5
7.5
–
7.5
–
39
89
–
70
0.3
5
600
–
0.8
0.4
–
70
5
2.5
10.5
10
–
–
3.9
300
11
15
–
1
1.45
5.40
350
–
185
–
Unit
mA
µA
V
V
V
V
mA
mA
ns
kΩ
V
µA
µs
V
V
V
mV
kΩ
µA
V
V/V
mV
µs
%
µs
µs
V/V
mV
mV
mV/µs
kΩ
V
mV
V
°C
°C
V
GH
V
GL
I
GPU
I
GPD
t
DT
R
GPD
V
OCLn
I
OCLn
t
OCLn
V
IH
V
IL
V
IL(SLEEPn)
V
HYS
R
PD
I
VREF
V
REF
A
V
V
OSSENSE
t
OFF
P
FD
t
BLK
t
pu
A
IOUT
V
OSAIOUT
V
SH(ACC)
V
DROOP
R
OUT(AIOUT)
V
BB(UVLO)
V
BB(UVLO,HYS)
V
DSTH
T
JTSD
ΔT
J
Temperature increasing
Recovery = T
JTSD
– ΔT
J
V
BB
rising
R
RC
= 30 kΩ, C
RC
= 1 nF
Internal PWM chop
R
RC
= 30 kΩ, C
RC
= 1 nF
Time until outputs are enabled
AIOUT/V
SENSE
, V
SENSE
= 50 to 200 mV
V
REF
/ V
SENSE
, V
REF
= 2.5 V
V
REF
= 2.5 V
SLEEPn input
I = 2 mA, overcurrent detected
V = 5 V, normal operation
–
–
300
2.0
–
–
–
30
–5
0
9.5
–10
–
–
2.1
–
9
–15
–
–
0.75
5.10
200
–
150
–
Specified limits are tested at a single temperature and assured over operating temperature range by design and characterization.
Target trip level = V
DSTH
= V
DRAIN
– V
Sx
(High Side On) or V
DSTH
= V
Sx
– V
SENSE
(Low Side On).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A4955
Full-Bridge PWM Gate Driver
Control Logic
IN1
x
0
0
1
1
0
1
IN2
x
0
1
0
1
1
0
SLEEPn
0
1
1
1
1
1
1
10 × V
SENSE
>
V
REF
x
x
false
false
x
true
true
OUTA
Z
Z
L
H
L
H/L
L
OUTB
Z
Z
H
L
L
L
H/L
Sleep (Standby) Mode
Coast
Reverse
Forward
Slow Decay SR (Brake)
Internal Chop Reverse, Mixed Decay *
Internal Chop Forward, Mixed Decay *
Function
* In fast decay, outputs change to high-Z state when load current approaches zero, to prevent reversal of current.
I
OCL
= V
REF
/ R
SENSE
/ 10
I_OUT
t
OCLn
OCLn
OCLn Output Flag
OCLn output function is described in the Functional Description section.
A
AIOUT
V
SENSE
A
B
B
C
300 µs
0V
V
SENSE
= V
REF
/10
0V
IN 1
(IN2 = High)
AIOUT Output
A. Internal OCL chop. AIOUT holds while SENSE voltage varies during the mixed-decay off-time.
B. INx chop. AIOUT holds while SENSE voltage drops to 0 V during slow decay.
C. Slow-decay timeout. AIOUT is forced to 0 V 300 µs after ENABLE goes low.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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