S i533 4
P
I N
-C
O N T R O L L E D
A
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- F
R E Q U E N C Y
, A
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U T P U T
Q
U A D
C
LOCK
G
ENERATOR
Features
Low-power MultiSynth technology
enables independent, any-frequency
synthesis on four differential output
drivers
Highly-configurable output drivers
support up to four differential outputs
or eight single-ended clock outputs or
a combination of both
Low phase jitter: 0.7 ps RMS typ
High-precision synthesis allows true
0 ppm frequency accuracy on all
outputs
Flexible input reference
crystal: 8 to 30 MHz
input: 5 to 200 MHz
SSTL/HSTL input: 5 to 350 MHz
Differential input: 5 to 710 MHz
CMOS
External
Independent output voltage per driver
1.5,
1.8,
1.8, 2.5, or 3.3 V
2.5, or 3.3 V
Independent core supply voltage
Frequency increment/decrement
feature enables glitchless frequency
adjustments in 1 ppm steps
Phase adjustment on each of the
output drivers with <20 ps steps
SSC on any or all outputs that is
compliant to PCI Express
Optional external feedback mode
allows zero-delay implementation
Loss-of-lock and loss-of-signal alarm
Simple pin control
Small size: 4x4 mm, 24-QFN
Low power: 45 mA core supply typ
Wide temperature range:
–40 to +85 °C
Contact Silicon Labs for custom
versions
Ordering Information:
See page 32.
Pin Assignments
Independently-configurable outputs
support any frequency or format
0.16 to 710 MHz
HCSL: 0.16 to 250 MHz
CMOS: 0.16 to 200 MHz
SSTL/HSTL: 0.16 to 350 MHz
LVPECL/LVDS:
Applications
Ethernet switch/router
PCI Express 2.0/3.0
Broadcast video/audio timing
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fibre Channel, SAN
Telecom line cards
1 GbE and 10 GbE
Description
The Si5334 is a high performance, low jitter clock generator capable of
synthesizing any frequency on each of the device's four differential output
clocks. The device accepts an external reference clock or crystal and generates
four differential clock outputs, each of which is independently configurable to
any frequency up to 350 MHz and select frequencies to 710 MHz. Using Silicon
Labs' patented MultiSynth technology, each output clock is generated with very
low jitter and zero ppm frequency error. To provide additional design flexibility,
each output clock is independently configurable to support any signal format and
reference voltage. The Si5334 provides low jitter frequency synthesis with
outstanding frequency flexibility in a space-saving 4 x 4 mm QFN package. The
device configuration is factory or field programmed and, upon power up, the
device will begin operation in the predefined configuration without user
intervention. The device supports operation from a 1.8, 2.5, or 3.3 V core supply.
Rev. 1.3
Copyright © 2017 by Silicon Laboratories
Si5334
Si5334
Functional Block Diagram
2
Rev. 1.3
Si5334
T
A B L E O F
C
O N T E N T S
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.2. Crystal/Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.3. Zero Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.4. Breakthrough MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.5. Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.6. Output Clock Initial Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.7. Output Clock Phase Increment and Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.8. Output Clock Frequency Increment and Decrement . . . . . . . . . . . . . . . . . . . . . . . . .17
2.9. R Divider Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.10. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.11. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.12. LOSLOL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.13. Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.14. Factory Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Device Pinout by Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5. Ordering Information and Standard Frequency Plans . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.2. Evaluation Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.3. Standard Frequency Plans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
7. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
8.1. Si5334 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
9. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Rev. 1.3
3
Si5334
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Ambient Temperature
Symbol
T
A
V
DD
V
DDOn
Test Condition
Min
–40
2.97
Typ
25
3.3
2.5
1.8
—
Max
85
3.63
2.75
1.98
3.63
Unit
°C
V
V
V
V
Core Supply Voltage
2.25
1.71
Output Buffer Supply
Voltage
1.4
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current
Core Supply Current
(Buffer Mode)
Symbol
I
DD
I
DDB
Test Condition
100 MHz on all outputs,
25 MHz refclk
50 MHz refclk
LVPECL, 710 MHz
LVDS, 710 MHz
HCSL, 250 MHz
2 pF load
CML, 350 MHz
SSTL, 350 MHz
Min
—
—
—
—
—
—
—
—
—
—
—
—
Typ
45
12
—
—
—
12
—
6
13
10
7
—
Max
60
—
30
8
20
—
19
9
18
14
10
19
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Output Buffer Supply Current
I
DDOx
CMOS, 50 MHz
15 pF load
1
CMOS, 200 MHz
1,2
3.3 V VDD0
CMOS, 200 MHz
1,2
2.5 V
CMOS, 200 MHz
1,2
1.8 V
HSTL, 350 MHz
Notes:
1.
Single CMOS driver active.
2.
Measured into a 5” 50
trace with 2 pF load.
4
Rev. 1.3
Si5334
Table 3. Performance Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
PLL Acquisition Time
PLL Tracking Range
PLL Loop Bandwidth
MultiSynth Frequency
Synthesis Resolution
CLKIN Loss of Signal Assert
Time
CLKIN Loss of Signal Deassert
Time
PLL Loss of Lock Detect Time
POR to Output Clock Valid
Input-to-Output Propagation
Delay
Output-Output Skew
Programmable Initial
Phase Offset
Phase Increment/Decrement
Accuracy
Phase Increment/Decrement
Range
Frequency range for phase
increment/decrement
Phase Increment/Decrement
Update Rate
Frequency Increment/
Decrement Step Size
Frequency Increment/
Decrement Range
Frequency Increment/
Decrement Update Rate
Symbol
t
ACQ
f
TRACK
f
BW
f
RES
t
LOS
t
LOS_b
t
LOL
t
RDY
t
PROP
t
DSKEW
P
OFFSET
P
STEP
P
RANGE
f
PRANGE
P
UPDATE
f
STEP
f
RANGE
f
UPDATE
Test Condition
Min
—
5000
—
Typ
—
20,000
1.6
0
2.6
0.2
5
—
2.5
—
—
—
—
—
—
—
—
—
Max
25
—
—
1
5
1
10
2
4
100
+45
20
+45
350
2
1500
See
Note
3
350
2
1500
Unit
ms
ppm
MHz
ppb
μs
μs
ms
ms
ns
ps
ns
ps
ns
MHz
kHz
ppm
MHz
kHz
Output frequency < Fvco/8
0
—
0.01
—
—
Buffer Mode
(PLL Bypass)
Rn divider = 1
1
—
—
–45
—
–45
—
Pin control
R divider not used
3
R divider not used
3
Pin control
2,3
—
1
—
—
Notes:
1.
Outputs at integer-related frequencies and using the same driver format.
2.
Keep MultiSynth output frequency between 5 MHz to Fvco/8.
3.
Only MultiSynth0 can have frequency inc/dec but MultiSynth0 can be routed to any output.
4.
Spread spectrum is only available on clock outputs that are at 100 MHz and have the Rn divider set to 1.
Rev. 1.3
5
FPGA/CPLD
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