w
Mono CODEC with Speaker Driver
DESCRIPTION
The WM8510 is a low power, high quality mono codec designed
for Voice over Internet Protocol (VoIP) and Digital Telephones.
The device integrates support for one pseudo-differential and
one single ended input (Handset Mic and Speaker Mic) and
includes drivers for speakers or headset, and mono line output,
making it ideal for Telephone designs. External component
requirements are reduced as no separate microphone or
earpiece amplifiers are required.
Advanced Sigma Delta Converters are used along with digital
decimation and interpolation filters to give high quality audio at
sample rates from 8 to 48kHz.
Additional digital filtering options are available in the ADC path,
to cater for application filtering such as ‘wind noise reduction’,
plus an advanced mixed signal ALC function with noise gate is
provided.
An on-chip PLL is provided to generate the required Master
Clock from an external reference clock. The PLL clock can also
be output if required elsewhere in the system.
The WM8510 operates at supply voltages from 2.5 to 3.6V,
although the digital supplies can operate at voltages down to
1.71V to save power. The speaker and mono outputs use a
separate supply of up to 5V which enables increased output
power if required. Different sections of the chip can also be
powered down under software control by way of the selectable
two or three wire control interface.
WM8510 is supplied in a convenient 28-lead SSOP package,
offering high levels of functionality in an easy to use package.
•
WM8510
FEATURES
•
•
•
•
•
•
•
•
•
Mono Codec:
Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1,
48kHz
DAC SNR 93dB, THD -84dB (‘A’-weighted @ 8 – 48kHz)
ADC SNR 90dB, THD -80dB (‘A’-weighted @ 8 – 48kHz)
On-chip Headphone/Speaker Driver with ‘cap-less’ connect
- 40mW output power into 16Ω / 3.3V SPKVDD
- BTL speaker drive 0.8W into 8Ω / 5V SPKVDD
Earpiece Line output
Multiple analog inputs, plus analog bypass path (0 or -10dB)
Mic Preamps:
Two Microphone Interfaces
- One pseudo-differential input with common mode
rejection
- One single ended input
- Programmable preamp gain
- Programmable ALC / Noise Gate in ADC path
Low-noise bias supplied for microphone
Other Features
•
Digital Playback Limiter
•
Programmable ADC High Pass Filter (wind noise reduction)
•
Programmable ADC Notch Filter
•
On-chip PLL
•
Low power, low voltage
- 2.5V to 3.6V (digital supplies: 1.71V to 3.6V)
- power consumption <10mW all-on 48kHz mode
•
28 lead SSOP package
APPLICATIONS
•
•
•
•
•
VoIP Telephones
Digital Telephones
Conference Speaker-phone
Mobile Telephone Hands-free Kits
General Purpose low power audio CODEC
BLOCK DIAGRAM
MIC2
20k
20k
I
2
S or PCM
INTERFACE
W
WM8510
NOISY
GND
Gains
: -12dB to
+35.25dB
ADC
DIGITAL
FILTERS
Volume
Limiter /
ALC
DAC
DIGITAL
FILTERS
Volume
Digital
Limiter
MICN
ADC
DAC
MONO OUT
Mic
MICP
IP PGA
IP BOOST/MIX
Wind Noise
Filters
-10dB or +0dB
Rbias
SIDETONE
-1
SPKOUTP
L - (-R)
-10dB or +0dB
= L+R
SPKOUTN
SPKR PGA
MICBIAS
4k
5k
25k
250k
25k
250k
PLL
CONTROL
INTERFACE
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up
at
http://www.wolfsonmicro.com/enews/
Production Data, September 2008, Rev 4.5
Copyright
©2008
Wolfson Microelectronics plc
WM8510
TABLE OF CONTENTS
Production Data
DESCRIPTION .......................................................................................................1
BLOCK DIAGRAM .................................................................................................1
FEATURES.............................................................................................................1
APPLICATIONS .....................................................................................................1
PIN CONFIGURATION...........................................................................................3
ORDERING INFORMATION ..................................................................................3
PIN DESCRIPTION ................................................................................................4
ABSOLUTE MAXIMUM RATINGS.........................................................................5
RECOMMENDED OPERATING CONDITIONS .....................................................5
ELECTRICAL CHARACTERISTICS ......................................................................6
TERMINOLOGY ............................................................................................................ 8
SIGNAL TIMING REQUIREMENTS .......................................................................9
SYSTEM CLOCK TIMING ............................................................................................. 9
AUDIO INTERFACE TIMING – MASTER MODE .......................................................... 9
AUDIO INTERFACE TIMING – SLAVE MODE............................................................ 10
CONTROL INTERFACE TIMING – 3-WIRE MODE .................................................... 11
CONTROL INTERFACE TIMING – 2-WIRE MODE .................................................... 12
DEVICE DESCRIPTION.......................................................................................13
INTRODUCTION ......................................................................................................... 13
INPUT SIGNAL PATH ................................................................................................. 14
ANALOGUE TO DIGITAL CONVERTER (ADC).......................................................... 19
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC) .......................................... 23
OUTPUT SIGNAL PATH ............................................................................................. 36
ANALOGUE OUTPUTS............................................................................................... 41
OUTPUT SWITCH ...................................................................................................... 46
DIGITAL AUDIO INTERFACES................................................................................... 48
AUDIO SAMPLE RATES ............................................................................................. 53
MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ............................................... 54
GENERAL PURPOSE INPUT/OUTPUT...................................................................... 56
CONTROL INTERFACE.............................................................................................. 56
RESETTING THE CHIP .............................................................................................. 57
POWER SUPPLIES .................................................................................................... 58
POWER MANAGEMENT ............................................................................................ 61
REGISTER MAP...................................................................................................64
REGISTER BITS BY ADDRESS ................................................................................. 65
DIGITAL FILTER CHARACTERISTICS ...............................................................76
TERMINOLOGY .......................................................................................................... 76
DAC FILTER RESPONSES......................................................................................... 77
ADC FILTER RESPONSES......................................................................................... 77
DE-EMPHASIS FILTER RESPONSES........................................................................ 78
HIGHPASS FILTER..................................................................................................... 79
APPLICATIONS INFORMATION .........................................................................80
RECOMMENDED EXTERNAL COMPONENTS .......................................................... 80
IMPORTANT NOTICE ..........................................................................................82
ADDRESS ................................................................................................................... 82
w
PD, Rev 4.5 ,September 2008
2
Production Data
WM8510
PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE
WM8510GEDS/V
WM8510GEDS/RV
Note:
Reel Quantity = 2,000
TEMPERATURE
RANGE
-40°C to +85°C
-40°C to +85°C
PACKAGE
28-lead SSOP
(Pb-free)
28-lead SSOP
(Pb-free, tape and reel)
MOISTURE SENSITIVITY
LEVEL
MSL3
MSL3
PACKAGE BODY
TEMPERATURE
260
o
C
260
o
C
w
PD, Rev 4.5, September 2008
3
WM8510
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
VMID
MICN
MICP
MICBIAS
NC
AVDD
AGND
AGND
DCVDD
DBVDD
DGND
ADCDAT
DACDAT
FRAME
BCLK
MCLK
CSB/GPIO
SCLK
SDIN
MODE
MONOOUT
SPKOUTP
SPKGND
SPKGND
SPKOUTN
SPKVDD
SPKVDD
MIC2
TYPE
Reference
Analog Input
Analog Input
Analog Output
NC
Supply
Supply
Supply
Supply
Supply
Supply
Digital Output
Digital Input
Digital Input/Output
Digital Input/Output
Digital Input
Digital Input/Output
Digital Input
Digital Input/Output
Digital Input
Analog Output
Analog Output
Supply
Supply
Analog Output
Supply
Supply
Analog Input
Microphone negative input
Microphone positive input (common mode)
Microphone Bias
No Connect
Analogue supply (feeds ADC, DAC and PLL)
Analogue ground (feeds ADC, DAC and PLL)
Analogue ground (feeds ADC, DAC and PLL)
Digital Core supply
Digital Buffer (Input/Output) supply
Digital ground
ADC Digital Audio Data Output
DAC Digital Audio Data Input
DAC and ADC Sample Rate Clock or Frame synch
Digital Audio Port Clock
Master Clock Input
DESCRIPTION
Decoupling for midrail reference voltage
Production Data
3-Wire MPU Chip Select or General Purpose Input/Output pin.
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
3-Wire MPU Data Input / 2-Wire MPU Data Input/Output
Control Interface Mode Selection Pin.
Mono Audio Output
Speaker Output Positive
Speaker ground (feeds speaker and mono output amps only)
Speaker ground (feeds speaker and mono output amps only)
Speaker Output Negative
Speaker supply (feeds speaker and mono output amps only)
Speaker supply (feeds speaker and mono output amps only)
Second Analog Input
w
PD, Rev 4.5 ,September 2008
4
Production Data
WM8510
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this
device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
DBVDD, DCVDD, AVDD supply voltages
SPKVDD supply voltage
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, T
A
Storage temperature after soldering
Notes
1.
2.
3.
Analogue and digital grounds must always be within 0.3V of each other.
All digital and analogue supplies are completely independent from each other.
When using the PLL, DCVDD should be
≥
1.9V
MIN
-0.3V
-0.3V
DGND -0.3V
AGND -0.3V
-40°C
-65°C
MAX
+3.63V
+7V
DVDD +0.3V
AVDD +0.3V
+85°C
+150°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supplies range
Speaker supply
Ground
Notes
1. DCVDD
≤
DBVDD at all times.
SYMBOL
DCVDD
DBVDD
AVDD
SPKVDD
DGND,AGND, SPKGND
TEST
CONDITIONS
MIN
1.71
1.71
2.5
2.5
0
TYP
MAX
3.6
3.6
3.6
5.5
UNIT
V
V
V
V
V
w
PD, Rev 4.5, September 2008
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
