Datasheet> 器件分类 > 开发板/开发套件/开发工具> CDBWM8994-M-1

CDBWM8994-M-1: 产品描述EVAL BD - WM8994 MINI EVAL BOARD; 产品类别开发板/开发套件/开发工具; 文件大小6MB，共363页; 制造商Cirrus Logic(凌云半导体); 官网地址http://www.cirrus.com; 标准

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CDBWM8994-M-1概述

EVAL BD - WM8994 MINI EVAL BOARD

CDBWM8994-M-1规格参数

参数名称	属性值
类型	音频
功能	CODEC
使用的 IC/零件	WM8994
所含物品	板

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WM8994

Multi-channel Audio Hub CODEC for Smartphones

DESCRIPTION

The WM8994 is a highly integrated ultra-low power hi-fi CODEC

designed for smartphones and other portable devices rich in

multimedia features.

An integrated stereo class D/AB speaker driver and class W

headphone driver minimize power consumption during audio

playback.

The device requires only two voltage supplies, with all other

internal supply rails generated from integrated LDOs.

Stereo full duplex asynchronous sample rate conversion and

multi-channel digital mixing combined with powerful analogue

mixing allow the device to support a huge range of different

architectures and use cases.

A fully programmable parametric EQ provides speaker

compensation and a dynamic range controller can be used in

the ADC or DAC paths for maintaining a constant signal level,

maximizing loudness and protecting speakers against

overloading and clipping.

A smart digital microphone interface provides power regulation,

a low jitter clock output and decimation filters for up to four

digital microphones. A MIC activity detect with interrupt is

available.

Fully differential internal architecture and on-chip RF noise filters

ensure a very high degree of noise immunity. Active ground loop

noise rejection and DC offset correction help prevent pop noise

and suppress ground noise on the headphone outputs.

FEATURES



Hi-fi 24-bit 4-channel DAC and 2-channel ADC

100dB SNR during DAC playback (‘A’ weighted)

Smart MIC interface

- Power, clocking and data input for up to four digital MICs

- High performance analogue MIC interface

- MIC activity detect & interrupt allows processor to sleep

2W stereo (2 x 2W) class D/AB speaker driver

Capless Class W headphone drivers

- Integrated charge pump

- 5.3mW total power for DAC playback to headphones

4 Line outputs (single-ended or differential)

BTL Earpiece driver

Digital audio interfaces for multi-processor architecture

- Asynchronous stereo duplex sample rate conversion

- Powerful mixing and digital loopback functions

ReTune

Mobile 5-band, 6-channel parametric EQ

Programmable dynamic range controller

Dual FLL provides all necessary clocks

- Self-clocking modes allow processor to sleep

- All standard sample rates from 8kHz to 96kHz

Active noise reduction circuits

- DC offset correction removes pops and clicks

- Ground loop noise cancellation

Integrated LDO regulators

72-ball W-CSP package (4.521 x 4.033 x 0.546mm)



APPLICATIONS



LDO1VDD

LDO1ENA

Smartphones and music phones

Portable navigation

Tablets

eBooks

Portable Media Players

CPVOUTN

CPVOUTP

SPKGND1

SPKGND2

SPKVDD1

SPKVDD2

HP2GND

CPGND

CPVDD

AVDD1

VMIDC

AGND

LDO2VDD

LDO2ENA

DCVDD

VREFC

AVDD2

VMIDC

DGND

AGND

LDO2

LDO1

CHARGE PUMP

CPCA

CPCB

HPOUT1L

HPOUT1R

IN1LN

IN1LP

IN2LN/DMICDAT1

IN2LP/VRXP

IN1RN

IN1RP

IN2RN/DMICDAT2

IN2RP/VRXN

HEADPHONE

DRIVERS

HPOUT1FB

HPOUT2P

HPOUT2N

4 Digital MIC

Channels

ANALOGUE

MIC

INTERFACE

INPUT

MIXERS

ADC

FILTERS

HIGH

PASS

FILTERS

ADC R

RECORD

DMICDAT1

DMICDAT2

DIGITAL MIC

INTERFACE

4 MIC

CHANNELS

HIGH

PASS

FILTERS

MIC Activity Detect

ADC

VOLUME

DAC

OUTPUT

MIXERS

EARPIECE

DRIVER

ADC L

MULTI-CHANNEL DIGITAL

MIXING

ReTune Mobile

PARAMETRIC EQUALISER

DYNAMIC RANGE CONTROL

3D STEREO ENHANCE

ASYNCHRONOUS SAMPLE

RATE CONVERSION

DAC

FILTERS

DAC

VOLUME

DAC

SPKOUTLP

SPKOUTLN

SPKOUTRP

SPKOUTRN

LOUDSPEAKER

DRIVERS

SPKMODE

DAC

LINEOUT1P

LINEOUT1N

DMICCLK

DAC

LINEOUT2P

LINEOUT2N

RECORD

LINE DRIVERS

MICBIAS1

Current

Detect

LINEOUTFB

GPIO

MCLK1

MCLK2

BCLK1

LRCLK1

MCLK1

MCLK2

BCLK2

LRCLK2

FLL1

MICBIAS2

Current

Detect

I2S/PCM #1

FLL2

I2S/PCM #2

I2S/PCM #3

CONTROL

INTERFACE

GPIO

GPIO11/BCLK3

GPIO10/LRCLK3

GPIO9/ADCDAT3

GPIO8/DACDAT3

CS/ADDR

SDA

SCLK

CIFMODE

DACDAT1

LRCLK1

ADCDAT1

ADCLRCLK1/GPIO1

BCLK1

GPIO7/ADCDAT2

GPIO6/ADCLRCLK2

GPIO5/DACDAT2

GPIO4/LRCLK2

GPIO3/BCLK2

http://www.cirrus.com



Cirrus Logic, Inc., 2010–2016

MCLK1

GPIO2/MCLK2

Rev 4.5

NOV ‘16

WM8994

TABLE OF CONTENTS

DESCRIPTION ................................................................................................................ 1

FEATURES ..................................................................................................................... 1

APPLICATIONS.............................................................................................................. 1

TABLE OF CONTENTS .................................................................................................. 2

BLOCK DIAGRAM ......................................................................................................... 6

PIN CONFIGURATION ................................................................................................... 7

ORDERING INFORMATION ........................................................................................... 7

PIN DESCRIPTION ......................................................................................................... 8

ABSOLUTE MAXIMUM RATINGS ............................................................................... 11

RECOMMENDED OPERATING CONDITIONS ............................................................ 12

THERMAL PERFORMANCE ........................................................................................ 13

ELECTRICAL CHARACTERISTICS ............................................................................ 14

INPUT SIGNAL LEVEL ............................................................................................................ 14

INPUT PIN RESISTANCE ........................................................................................................ 15

PROGRAMMABLE GAINS....................................................................................................... 17

OUTPUT DRIVER CHARACTERISTICS ................................................................................. 18

ADC INPUT PATH PERFORMANCE....................................................................................... 19

DAC OUTPUT PATH PERFORMANCE ................................................................................... 20

BYPASS PATH PERFORMANCE............................................................................................ 23

MULTI-PATH CROSSTALK ..................................................................................................... 25

DIGITAL INPUT / OUTPUT ...................................................................................................... 27

DIGITAL FILTER CHARACTERISTICS ................................................................................... 27

MICROPHONE BIAS CHARACTERISTICS ............................................................................. 28

MISCELLANEOUS CHARACTERISTICS ................................................................................ 29

TERMINOLOGY ....................................................................................................................... 30

TYPICAL PERFORMANCE .......................................................................................... 31

TYPICAL POWER CONSUMPTION ........................................................................................ 31

TYPICAL SIGNAL LATENCY ................................................................................................... 32

SPEAKER DRIVER PERFORMANCE ..................................................................................... 33

SIGNAL TIMING REQUIREMENTS ............................................................................. 34

SYSTEM CLOCKS & FREQUENCY LOCKED LOOP (FLL) .................................................... 34

AUDIO INTERFACE TIMING ................................................................................................... 35

DIGITAL MICROPHONE (DMIC) INTERFACE TIMING ................................................................................................................35

DIGITAL AUDIO INTERFACE - MASTER MODE .........................................................................................................................36

DIGITAL AUDIO INTERFACE - SLAVE MODE .............................................................................................................................37

DIGITAL AUDIO INTERFACE - TDM MODE ................................................................................................................................38

CONTROL INTERFACE TIMING ............................................................................................. 39

2-WIRE (I2C) CONTROL MODE ...................................................................................................................................................39

3-WIRE (SPI) CONTROL MODE ...................................................................................................................................................40

4-WIRE (SPI) CONTROL MODE ...................................................................................................................................................41

DEVICE DESCRIPTION ............................................................................................... 42

INTRODUCTION ...................................................................................................................... 42

ANALOGUE INPUT SIGNAL PATH ......................................................................................... 44

MICROPHONE INPUTS ................................................................................................................................................................45

MICROPHONE BIAS CONTROL ..................................................................................................................................................45

MICROPHONE CURRENT DETECT ............................................................................................................................................46

LINE AND VOICE CODEC INPUTS ..............................................................................................................................................47

INPUT PGA ENABLE ....................................................................................................................................................................48

INPUT PGA CONFIGURATION ....................................................................................................................................................48

Rev 4.5

WM8994

INPUT PGA VOLUME CONTROL .................................................................................................................................................50

INPUT MIXER ENABLE.................................................................................................................................................................53

INPUT MIXER CONFIGURATION AND VOLUME CONTROL .....................................................................................................53

DIGITAL MICROPHONE INTERFACE .................................................................................... 57

DIGITAL PULL-UP AND PULL-DOWN ..........................................................................................................................................60

ANALOGUE TO DIGITAL CONVERTER (ADC) ...................................................................... 60

ADC CLOCKING CONTROL .........................................................................................................................................................61

DIGITAL CORE ARCHITECTURE ........................................................................................... 62

DIGITAL MIXING ...................................................................................................................... 64

AUDIO INTERFACE 1 (AIF1) OUTPUT MIXING ...........................................................................................................................65

DIGITAL SIDETONE MIXING ........................................................................................................................................................66

DIGITAL SIDETONE VOLUME AND FILTER CONTROL .............................................................................................................66

DAC OUTPUT DIGITAL MIXING ...................................................................................................................................................69

AUDIO INTERFACE 2 (AIF2) DIGITAL MIXING ...........................................................................................................................70

ULTRASONIC (4FS) AIF OUTPUT MODE ....................................................................................................................................70

DYNAMIC RANGE CONTROL (DRC) ..................................................................................... 72

DRC COMPRESSION / EXPANSION / LIMITING.........................................................................................................................73

GAIN LIMITS..................................................................................................................................................................................75

DYNAMIC CHARACTERISTICS ...................................................................................................................................................75

ANTI-CLIP CONTROL ...................................................................................................................................................................75

QUICK RELEASE CONTROL .......................................................................................................................................................76

SIGNAL ACTIVITY DETECT .........................................................................................................................................................76

DRC REGISTER CONTROLS .......................................................................................................................................................76

RETUNE MOBILE PARAMETRIC EQUALIZER (EQ) .............................................................. 86

DEFAULT MODE (5-BAND PARAMETRIC EQ) ...........................................................................................................................86

RETUNE MOBILE MODE ..............................................................................................................................................................89

EQ FILTER CHARACTERISTICS .................................................................................................................................................90

3D STEREO EXPANSION ....................................................................................................... 91

DIGITAL VOLUME AND FILTER CONTROL ........................................................................... 92

AIF1 - OUTPUT PATH VOLUME CONTROL ................................................................................................................................92

AIF1 - OUTPUT PATH HIGH PASS FILTER .................................................................................................................................95

AIF1 - INPUT PATH VOLUME CONTROL ....................................................................................................................................96

AIF1 - INPUT PATH SOFT MUTE CONTROL ..............................................................................................................................99

AIF1 - INPUT PATH MONO MIX AND DE-EMPHASIS FILTER .................................................................................................100

AIF2 - OUTPUT PATH VOLUME CONTROL ..............................................................................................................................101

AIF2 - OUTPUT PATH HIGH PASS FILTER ...............................................................................................................................102

AIF2 - INPUT PATH VOLUME CONTROL ..................................................................................................................................103

AIF2 - INPUT PATH SOFT MUTE CONTROL ............................................................................................................................103

AIF2 - INPUT PATH MONO MIX AND DE-EMPHASIS FILTER .................................................................................................104

DIGITAL TO ANALOGUE CONVERTER (DAC) .................................................................... 105

DAC CLOCKING CONTROL .......................................................................................................................................................105

DAC DIGITAL VOLUME ..............................................................................................................................................................107

DAC SOFT MUTE AND SOFT UN-MUTE ...................................................................................................................................110

ANALOGUE OUTPUT SIGNAL PATH ................................................................................... 112

OUTPUT SIGNAL PATHS ENABLE ............................................................................................................................................113

HEADPHONE SIGNAL PATHS ENABLE ....................................................................................................................................115

OUTPUT MIXER CONTROL .......................................................................................................................................................117

SPEAKER MIXER CONTROL .....................................................................................................................................................121

OUTPUT SIGNAL PATH VOLUME CONTROL ...........................................................................................................................124

SPEAKER BOOST MIXER ..........................................................................................................................................................129

EARPIECE DRIVER MIXER ........................................................................................................................................................130

LINE OUTPUT MIXERS ..............................................................................................................................................................131

CHARGE PUMP ..................................................................................................................... 134

DC SERVO ............................................................................................................................. 136

DC SERVO ENABLE AND START-UP .......................................................................................................................................136

Rev 4.5

WM8994

DC SERVO ACTIVE MODES ......................................................................................................................................................138

GPIO / INTERRUPT OUTPUTS FROM DC SERVO ...................................................................................................................140

ANALOGUE OUTPUTS ......................................................................................................... 140

SPEAKER OUTPUT CONFIGURATIONS ...................................................................................................................................140

HEADPHONE OUTPUT CONFIGURATIONS .............................................................................................................................143

EARPIECE DRIVER OUTPUT CONFIGURATIONS ...................................................................................................................144

LINE OUTPUT CONFIGURATIONS ............................................................................................................................................144

GENERAL PURPOSE INPUT/OUTPUT ................................................................................ 147

GPIO CONTROL .........................................................................................................................................................................148

GPIO FUNCTION SELECT .........................................................................................................................................................151

BUTTON DETECT (GPIO INPUT) ...............................................................................................................................................152

LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT (GPIO OUTPUT) ................................................................................................................152

SDOUT (4-WIRE SPI CONTROL INTERFACE DATA) ...............................................................................................................153

INTERRUPT (IRQ) STATUS OUTPUT ........................................................................................................................................153

OVER-TEMPERATURE DETECTION.........................................................................................................................................153

ACCESSORY DETECTION (MICBIAS CURRENT DETECTION) ..............................................................................................154

FREQUENCY LOCKED LOOP (FLL) LOCK STATUS OUTPUT ................................................................................................155

SAMPLE RATE CONVERTER (SRC) LOCK STATUS OUTPUT ...............................................................................................155

DYNAMIC RANGE CONTROL (DRC) SIGNAL ACTIVITY DETECTION ....................................................................................155

CONTROL WRITE SEQUENCER STATUS DETECTION ..........................................................................................................157

DIGITAL CORE FIFO ERROR STATUS DETECTION................................................................................................................158

OPCLK CLOCK OUTPUT ............................................................................................................................................................158

FLL CLOCK OUTPUT ..................................................................................................................................................................158

INTERRUPTS ........................................................................................................................ 159

DIGITAL AUDIO INTERFACE ................................................................................................ 166

MASTER AND SLAVE MODE OPERATION ...............................................................................................................................167

OPERATION WITH TDM .............................................................................................................................................................167

AUDIO DATA FORMATS (NORMAL MODE) ..............................................................................................................................168

AUDIO DATA FORMATS (TDM MODE) .....................................................................................................................................171

DIGITAL AUDIO INTERFACE CONTROL ............................................................................. 173

AIF1 - MASTER / SLAVE AND TRI-STATE CONTROL ..............................................................................................................173

AIF1 - SIGNAL PATH ENABLE ...................................................................................................................................................174

AIF1 - BCLK AND LRCLK CONTROL .........................................................................................................................................174

AIF1 - DIGITAL AUDIO DATA CONTROL ...................................................................................................................................177

AIF1 - MONO MODE ...................................................................................................................................................................178

AIF1 - COMPANDING .................................................................................................................................................................179

AIF1 - LOOPBACK ......................................................................................................................................................................180

AIF2 - MASTER / SLAVE AND TRI-STATE CONTROL ..............................................................................................................181

AIF2 - SIGNAL PATH ENABLE ...................................................................................................................................................182

AIF2 - BCLK AND LRCLK CONTROL .........................................................................................................................................182

AIF2 - DIGITAL AUDIO DATA CONTROL ...................................................................................................................................185

AIF2 - MONO MODE ...................................................................................................................................................................186

AIF2 - COMPANDING .................................................................................................................................................................187

AIF2 - LOOPBACK ......................................................................................................................................................................187

AUDIO INTERFACE AIF3 CONFIGURATION ............................................................................................................................188

DIGITAL PULL-UP AND PULL-DOWN ........................................................................................................................................190

CLOCKING AND SAMPLE RATES........................................................................................ 191

AIF1CLK ENABLE .......................................................................................................................................................................192

AIF1 CLOCKING CONFIGURATION ..........................................................................................................................................193

AIF2CLK ENABLE .......................................................................................................................................................................195

AIF2 CLOCKING CONFIGURATION ..........................................................................................................................................195

MISCELLANEOUS CLOCK CONTROLS ....................................................................................................................................197

BCLK AND LRCLK CONTROL ....................................................................................................................................................200

CONTROL INTERFACE CLOCKING ..........................................................................................................................................201

FREQUENCY LOCKED LOOP (FLL) ..........................................................................................................................................201

Rev 4.5

WM8994

FREE-RUNNING FLL CLOCK .....................................................................................................................................................206

GPIO OUTPUTS FROM FLL .......................................................................................................................................................207

EXAMPLE FLL CALCULATION...................................................................................................................................................207

EXAMPLE FLL SETTINGS ..........................................................................................................................................................208

SAMPLE RATE CONVERSION ............................................................................................. 209

SAMPLE RATE CONVERTER 1 (SRC1) ....................................................................................................................................209

SAMPLE RATE CONVERTER 2 (SRC2) ....................................................................................................................................209

SAMPLE RATE CONVERTER RESTRICTIONS ........................................................................................................................209

SAMPLE RATE CONVERTER CONFIGURATION ERROR INDICATION .................................................................................211

CONTROL INTERFACE......................................................................................................... 212

SELECTION OF CONTROL INTERFACE MODE .......................................................................................................................212

2-WIRE (I2C) CONTROL MODE .................................................................................................................................................213

3-WIRE (SPI) CONTROL MODE .................................................................................................................................................216

4-WIRE (SPI) CONTROL MODE .................................................................................................................................................217

CONTROL WRITE SEQUENCER.......................................................................................... 218

INITIATING A SEQUENCE..........................................................................................................................................................218

PROGRAMMING A SEQUENCE ................................................................................................................................................219

DEFAULT SEQUENCES .............................................................................................................................................................222

LDO REGULATORS .............................................................................................................. 228

POP SUPPRESSION CONTROL .......................................................................................... 231

DISABLED LINE OUTPUT CONTROL ........................................................................................................................................231

LINE OUTPUT DISCHARGE CONTROL ....................................................................................................................................232

VMID REFERENCE DISCHARGE CONTROL ............................................................................................................................232

INPUT VMID CLAMPS ................................................................................................................................................................232

REFERENCE VOLTAGES AND MASTER BIAS ................................................................... 233

POWER MANAGEMENT ....................................................................................................... 235

THERMAL SHUTDOWN ........................................................................................................ 241

POWER ON RESET............................................................................................................... 241

QUICK START-UP AND SHUTDOWN .................................................................................. 244

SOFTWARE RESET AND DEVICE ID................................................................................... 245

REGISTER MAP ......................................................................................................... 246

REGISTER BITS BY ADDRESS ............................................................................................ 256

APPLICATIONS INFORMATION ............................................................................... 349

RECOMMENDED EXTERNAL COMPONENTS .................................................................... 349

AUDIO INPUT PATHS .................................................................................................................................................................349

HEADPHONE OUTPUT PATH ....................................................................................................................................................350

EARPIECE DRIVER OUTPUT PATH ..........................................................................................................................................351

LINE OUTPUT PATHS ................................................................................................................................................................351

POWER SUPPLY DECOUPLING ...............................................................................................................................................352

CHARGE PUMP COMPONENTS ...............................................................................................................................................353

MICROPHONE BIAS CIRCUIT ...................................................................................................................................................353

CLASS D SPEAKER CONNECTIONS ........................................................................................................................................354

RECOMMENDED EXTERNAL COMPONENTS DIAGRAM .......................................................................................................356

DIGITAL AUDIO INTERFACE CLOCKING CONFIGURATIONS........................................... 357

PCB LAYOUT CONSIDERATIONS ....................................................................................... 360

CLASS D LOUDSPEAKER CONNECTION ................................................................................................................................360

PACKAGE DIMENSIONS ........................................................................................... 361

IMPORTANT NOTICE ................................................................................................ 362

REVISION HISTORY .................................................................................................. 363

Rev 4.5

CDBWM8994-M-1相似产品对比

	CDBWM8994-M-1	CDKWM8994-S-1
描述	EVAL BD - WM8994 MINI EVAL BOARD	KIT - WM8994 KIT CDB6220 MB DC
类型	音频	音频
功能	CODEC	CODEC
使用的 IC/零件	WM8994	WM8994
所含物品	板	板

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