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DESCRIPTION
The WM8750BL is a low power, high quality stereo CODEC
designed for portable digital audio applications.
The device integrates complete interfaces to stereo or mono
microphones and a stereo headphone. External component
requirements are drastically reduced as no separate
microphone or headphone amplifiers are required.
Advanced on-chip digital signal processing performs graphic
equaliser, 3-D sound enhancement and automatic level
control for the microphone or line input.
The WM8750BL can operate as a master or a slave, with
various master clock frequencies including 12 or 24MHz for
USB devices, or standard 256f
s
rates like 12.288MHz and
24.576MHz. Different audio sample rates such as 96kHz,
48kHz, 44.1kHz are generated directly from the master
clock without the need for an external PLL.
The WM8750BL operates at supply voltages down to 1.8V,
although the digital core can operate at voltages down to
1.42V to save power, and the maximum for all supplies is
3.6 Volts. Different sections of the chip can also be powered
down under software control.
The WM8750BL is supplied in a very small and thin 5x5mm
QFN package, ideal for use in hand-held and portable
systems.
WM8750BL
Stereo CODEC for Portable Audio Applications
FEATURES
DAC SNR 97dB (‘A’ weighted), THD -85dB at 48kHz, 3.3V
ADC SNR 88dB (‘A’ weighted), THD -80dB at 48kHz, 3.3V
Complete Stereo / Mono Microphone Interface
- Programmable ALC / Noise Gate
On-chip 400mW BTL Speaker Driver (mono)
On-chip Headphone Driver
- >40mW output power on 16 / 3.3V
- THD –73dB at 5mW, SNR 98dB with 16 load
- No DC blocking capacitors required (capless mode)
Separately mixed mono output
Digital Graphic Equaliser
Low Power
- 6 mW stereo playback (1.8V / 1.5V supplies)
- 13 mW record & playback (1.8V / 1.5V supplies)
Low Supply Voltages
- Analogue 1.8V to 3.6V
- Digital core: 1.42V to 3.6V
- Digital I/O: 1.8V to 3.6V
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48,
88.2, 96kHz generated internally from master clock
5x5x0.9mm QFN package
APPLICATIONS
Portable Media Player
Mobile phone handsets
Mobile gaming
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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Production Data, August 2012, Rev 4.1
Copyright
2012
Wolfson Microelectronics plc
WM8750BL
TABLE OF CONTENTS
Production Data
DESCRIPTION ................................................................................................................... 1
FEATURES ......................................................................................................................... 1
APPLICATIONS ................................................................................................................. 1
BLOCK DIAGRAM ............................................................................................................. 1
TABLE OF CONTENTS ..................................................................................................... 2
PIN CONFIGURATION ....................................................................................................... 3
ORDERING INFORMATION .............................................................................................. 3
PIN DESCRIPTION ............................................................................................................ 4
ABSOLUTE MAXIMUM RATINGS..................................................................................... 5
RECOMMENDED OPERATION CONDITIONS ................................................................. 5
ELECTRICAL CHARACTERISTICS .................................................................................. 6
TYPICAL PERFORMANCE................................................................................................ 8
POWER CONSUMPTION............................................................................................................... 8
OUTPUT DRIVERS ........................................................................................................................ 9
OUTPUT PGA’S LINEARITY ........................................................................................................ 10
SIGNAL TIMING REQUIREMENTS ................................................................................. 11
SYSTEM CLOCK TIMING ............................................................................................................ 11
AUDIO INTERFACE TIMING – MASTER MODE ......................................................................... 11
AUDIO INTERFACE TIMING – SLAVE MODE ............................................................................ 12
INTERNAL POWER ON RESET CIRCUIT ...................................................................... 15
DEVICE DESCRIPTION ................................................................................................... 16
INTRODUCTION ........................................................................................................................... 16
INPUT SIGNAL PATH ................................................................................................................... 16
AUTOMATIC LEVEL CONTROL (ALC)........................................................................................ 23
OUTPUT SIGNAL PATH............................................................................................................... 27
ANALOGUE OUTPUTS ................................................................................................................ 32
ENABLING THE OUTPUTS.......................................................................................................... 34
HEADPHONE SWITCH ................................................................................................................ 34
THERMAL SHUTDOWN ............................................................................................................... 35
HEADPHONE OUTPUT................................................................................................................ 36
DIGITAL AUDIO INTERFACE ...................................................................................................... 37
AUDIO INTERFACE CONTROL ................................................................................................... 41
CLOCKING AND SAMPLE RATES .............................................................................................. 43
CONTROL INTERFACE ............................................................................................................... 45
POWER SUPPLIES ...................................................................................................................... 46
POWER MANAGEMENT .............................................................................................................. 46
REGISTER MAP ............................................................................................................... 49
DIGITAL FILTER CHARACTERISTICS ........................................................................... 50
TERMINOLOGY ............................................................................................................................ 50
DAC FILTER RESPONSES .......................................................................................................... 51
ADC FILTER RESPONSES .......................................................................................................... 52
DE-EMPHASIS FILTER RESPONSES ........................................................................................ 53
HIGHPASS FILTER ...................................................................................................................... 54
APPLICATIONS INFORMATION ..................................................................................... 55
RECOMMENDED EXTERNAL COMPONENTS .......................................................................... 55
LINE INPUT CONFIGURATION ................................................................................................... 56
MICROPHONE INPUT CONFIGURATION .................................................................................. 56
MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS ........................................................ 56
POWER MANAGEMENT EXAMPLES ......................................................................................... 57
IMPORTANT NOTICE ...................................................................................................... 59
ADDRESS ..................................................................................................................................... 59
REVISION HISTORY ........................................................................................................ 60
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Production Data
WM8750BL
PIN CONFIGURATION
ORDERING INFORMATION
ORDER CODE
WM8750CBLGEFL
WM8750CBLGEFL/R
Note:
Reel quantity = 3500
TEMPERATURE
RANGE
-25C to +85C
-25C to +85C
PACKAGE
32-lead QFN (5x5x0.9mm)
(Pb-free)
32-lead QFN (5x5x0.9mm)
(Pb-free, tape and reel)
MOISTURE
SENSITIVITY LEVEL
MSL1
MSL1
PEAK SOLDERING
TEMPERATURE
260 C
260 C
o
o
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WM8750BL
PIN DESCRIPTION
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note:
It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
NAME
MCLK
DCVDD
DBVDD
DGND
BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
MONOOUT
OUT3
ROUT1
LOUT1
HPGND
ROUT2
LOUT2
HPVDD
AVDD
AGND
VREF
VMID
MICBIAS
RINPUT3 /
HPDETECT
LINPUT3
RINPUT2
LINPUT2
RINPUT1
LINPUT1
MODE
CSB
SDIN
SCLK
Supply
Supply
Supply
Digital Input / Output
Digital Input
Digital Input / Output
Digital Output
Digital Input / Output
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Supply
Analogue Output
Analogue Output
Supply
Supply
Supply
Analogue Output
Analogue Output
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Digital Input
Digital Input
Digital Input/Output
Digital Input
TYPE
Digital Input
Master Clock
Digital Core Supply
Digital Buffer (I/O) Supply
DESCRIPTION
Production Data
Digital Ground (return path for both DCVDD and DBVDD)
Audio Interface Bit Clock
DAC Digital Audio Data
Audio Interface Left / Right Clock/Clock Out
ADC Digital Audio Data
Audio Interface Left / Right Clock
Mono Output
Analogue Output 3 (can be used as Headphone Pseudo Ground)
Right Output 1 (Line or Headphone)
Left Output 1 (Line or Headphone)
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2)
Right Output 1 (Line or Headphone or Speaker)
Left Output 1 (Line or Headphone or Speaker)
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT)
Analogue Supply
Analogue Ground (return path for AVDD)
Reference Voltage Decoupling Capacitor
Midrail Voltage Decoupling Capacitor
Microphone Bias
Right Channel Input 3 or Headphone Plug-in Detection
Left Channel Input 3
Right Channel Input 2
Left Channel Input 2
Right Channel Input 1
Left Channel Input 1
Control Interface Selection
Chip Select / Device Address Selection
Control Interface Data Input / 2-wire Acknowledge output
Control Interface Clock Input
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Production Data
WM8750BL
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Supply voltages
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, T
A
Storage temperature after soldering
Notes
1.
2.
3.
Analogue and digital grounds must always be within 0.3V of each other.
All digital and analogue supplies are independent of each other.
DCVDD must be less than or equal to AVDD and DBVDD.
MIN
-0.3V
DGND -0.3V
AGND -0.3V
-25C
-65C
MAX
+3.63V
DBVDD +0.3V
AVDD +0.3V
+85C
+150C
RECOMMENDED OPERATION CONDITIONS
PARAMETER
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supplies range
Ground
SYMBOL
DCVDD
DBVDD
AVDD, HPVDD
DGND,AGND, HPGND
MIN
1.42
1.7
1.8
0
TYP
MAX
3.6
3.6
3.6
UNIT
V
V
V
V
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