Si3483
P
OWER
M
ANAGEMENT
C
ON TROLLER
Features
Pin Assignments
Enables use of smaller power
supplies for up to 64-port PoE
systems with Si3459 and Si3454
PSE interface ICs
Can operate with or without a host
Configuration save capability
Pin-selectable SPI or UART interface
Pin-selectable UART data rate
Fully-compliant with IEEE 802.3-AT
Types I and II
Supports classification-based and
LLDP power negotiation
Supports individual port priority and
port configuration
Supports Power supply status from
up to 3 power supplies
24-pin Quad flat pack package
4x4 mm PCB footprint; RoHS
complaint
Extended temperature operating
range (–40 to +85 °C)
24-Pin QFN
RSVD
20
MOSI
NSS
INT
19
18 SDA
17 SCL
16 BAUD0
15 BAUD1
14 BAUD2
13 PSLCT
10
11
12
7
8
9
PS1
RX
21
PS3
TX
22
RSVD
24
1
2
3
4
5
6
23
MISO
SCK
GND
VDD
RST
RSVD
Top View
(Pads on Bottom of Package)
RESET_PSE
RSVD
Applications
Power over Ethernet Endpoint
Industrial automation systems
switches and Midspans
Networked audio
Supports high-power PDs, such as
:
IP Phone Systems and iPBXs
Pan/Tilt/Zoom security cameras
Wireless Access Points
Security and RFID systems
See "5. Pin Descriptions" on page 43.
Description
The Si3483 is a power manager intended for use with the Si3459 Power over
Ethernet (PoE) controllers for power management of up to 64 ports with three
power sources.
The Si3459 is capable of delivering over 30 W per port, which means that, in a 24-
or 48-port system, a very large power supply would have to be used to avoid
overload. Typically, not all ports are used at full power; so, a smaller power supply
can be used along with the Si3483 power management controller.
Use of the Si3483 power manager greatly simplifies system implementation of
power management. The Si3483 power management controller is programmed
via a SPI or UART interface to set the system power supply capacity, the port
power configuration (Type 1: 15.4 W, or high-power Type 2: 30 W) ports, the port
priority, the detection timing (Alternative A or Alternative B), and the fault recovery
protocol. Once programmed, the configuration data can be saved, and the Si3483
can work without host intervention. Port and overall status information is available
and continuously updated.
The Si3483 uses the real-time overload and current monitoring capability of the
Si3459 to manage power shared among up to 64 ports. Power management is
selectable between grant-based or consumption-based algorithms in order to
supply power to the greatest number of ports.
In high-reliability systems, multiple power supplies are often connected to provide
redundancy, which further increases the power supply monitoring requirements.
The Si3483 can manage up to three power supplies automatically, enabling or
disabling ports in priority order.
Confidential Rev. 1.1 6/15
Copyright © 2015 by Silicon Laboratories
PS2
Si3483
Si3483
Functional Block Diagram
Si3483 Application Diagram
MCU or
Host Controller
UART or SPI
Si8631
Digital Isolator
Power Supply Present
Power Supply 1
Power Supply 2
Power Supply 3
Si3483 Power
Management
Controller
I
2
C
Select
UART or SPI
UART
Baud Rate
Power
Si3459 Port Controller
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
Si3459 Port Controller
PD
PD
PD
PD
PD
PD
PD
Si3459 Port Controller
PD
PD
PD
PD
PD
PD
PD
2
Confidential Rev. 1.1
Si3483
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1. Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. Hardware Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Serial Packet Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1. Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2. SPP Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Power Manager API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1. System Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2. Port Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3. System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4. Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.5. System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6. Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.7. Power Supply Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.8. Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.9. Return Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7. Package Outline: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
9. Top Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Confidential Rev. 1.1
3
Si3483
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Description
Operating Temperature
Range
V
DD
Supply Voltage
Symbol
T
A
V
DD
Test Condition
No airflow
All operating modes
Min
–40
2.7
Typ
—
—
Max
85
3.6
Unit
°C
V
Table 2. Absolute Maximum Ratings
Parameter
Ambient Temperature
under Bias
Storage Temperature
Voltage on any I/O with
Respect to GND
Voltage on V
DD
with
Respect to GND
V
DD
>2.2 V
Test Condition
Min
–55
–65
–0.3
–0.3
Typ
—
—
—
—
Max
125
150
5.8
4.2
Unit
°C
°C
V
V
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the devices at those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 3. Electrical Characteristics
Parameter
Input High
Input Low
Input Leakage Current
Output Low
(MOSI, TX, SCL, and SDA)
Output High
(MOSI, TX)
V
DD
Current
Symbol
V
IH
V
IL
I
IL
V
OL
V
OH
I
DD
Test Condition
Input pins:
RST, SCK, MOSI, NSS,
RX, PSn, BAUDn,
SLCTIN, SCL, SDA
I
OL
= 8.5 mA
I
OH
= –3 mA
VDD = 3.0 V*
VDD = 3.6 V*
Min
2.0
—
—
—
V
DD
–0.7
—
Typ
—
—
—
—
—
—
Max
—
0.8
±1
0.6
—
8.6
12.1
Unit
V
V
uA
V
V
mA
*Note:
V
DD
= 2.7 to 3.6 V, –40 to 85 °C unless otherwise noted.
4
Confidential Rev. 1.1
Si3483
Table 4. Timing Requirements
Parameter
SPI Timing Requirements (See Figure 1)
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
NSS Rising to MISO High Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
Maximum SPI Clock Speed
UART Requirements (See Figure 2)
Deviation of Tx Transmit Speed from Pin-programmed Value
Deviation of Rx receive Speed from Pin-programmed Value
∆FTx
∆FRx
–3
–4
+3
+4
%
%
T
SE
T
SD
T
SEZ
T
SDZ
T
CKH
T
CKL
T
SIS
T
SIH
T
SCH
F
MAX
84
84
—
—
210
210
84
84
—
—
—
—
168
168
—
—
—
—
168
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Symbol
Min
Max
Unit
T
SE
T
CKH
T
CKL
T
SD
SCK
T
SIH
MOSI
MSB
T
SIS
MISO
T
SEZ
NSS
MSB
Bit 6
Bit 5
T
SCH
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T
SDZ
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Figure 1. SPI Timing Diagram
MARK
SPACE
BIT TIMES
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP
BIT
BIT SAMPLING
Figure 2. UART Timing Diagram
Confidential Rev. 1.1
5
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