Model 578
Stratum 3
Temperature Compensated Crystal Oscillator
FEATURES
Clipped Sine Output
Optional Voltage Control for Frequency Tuning [VCTCXO]
7.0mmx5.0mm Surface Mount Package
Frequency Range 5 – 52 MHz
Fundamental Crystal Design
Operating Voltage, +3.0Vdc, +3.3Vdc or +5.0Vdc
Overall Frequency Stability ±4.6ppm
Operating Temperature to -40°C to +85°C
Tape & Reel Packaging Standard, EIA-418
RoHS/Green Compliant [6/6]
APPLICATIONS
The Model 578, a quartz based analog TCXO with Clipped Sine output and optional frequency tuning, is suitable for
applications requiring Stratum 3 performance such as base stations, Microcells, Femtocells, 1588 and Synchronous
Ethernet timing, wireless communications, test and measurement.
ORDERING INFORMATION
578
SUPPLY VOLTAGE
R = +3.0Vdc
L = +3.3Vdc
S = +5.0Vdc
FREQUENCY
Product Frequency Code
[3 digits]
Refer to document 016-1454-0,
Frequency Code Tables.
PACKAGING OPTIONS
T - 1k pcs./reel
FREQUENCY TUNING [AFC]
T = No AFC [TCXO]
A = ±5ppm - ±8ppm [VCTCXO]
OPERATING TEMPERATURE RANGE
C = -20°C to +70°C
I = -40°C to +85°C
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
PACKAGING INFORMATION
[reference]
Device quantity is 1k pcs. maximum per 180mm reel.
17.5
2.0
4.0
8.0
Ø1.50
1.75
2.40
2.10
Ø13
120°
8.40
7.90
16.0
Ø60
Ø180
5.70
5.40
DIRECTION OF FEED
Dimensions in Millimeters
Ø23
Dimensions in Millimeters
Document No. 008-0344-0
Page 1 - 3
Rev. B
www.ctscorp.com
Model 578
Stratum 3 TCXO/VC-TCXO – Clipped Sine
ELECTRICAL CHARACTERISTICS
PARAMETER
Maximum Supply Voltage
Maximum Control Voltage
Storage Temperature
Operating Temperature
Order Code 'C'
Order Code 'I'
Frequency Range
Supply Voltage
Order Code 'R'
Order Code 'L'
Order Code 'S'
Supply Current
Frequency Stability
Overall Frequency Stability
vs. Initial Calibration
vs. Operating Temperature
vs. Supply Voltage
vs. Load
vs. Aging
Holdover
Control Voltage
Frequency Tuning
[VCTCXO Only]
V
C
Input Impedance
Output Waveform
Output Voltage Levels
Output Load
Output Duty Cycle
Start Up Time
Enable Function
Enable Input Voltage
Disable Input Voltage
Phase Noise
1
SYMBOL
V
C C
V
C
T
S TG
T
A
f
O
V
C C
I
C C
∆f/f
O
±5%
CONDITIONS
-
-
-
-
-
MIN
-0.6
-0.5
-40
-20
-40
5
2.85
3.14
4.75
-
-
-
-
-
-
-
-
0.5
100
TYP
-
-
-
+25
-
3.0
3.3
5.0
-
-
-
-
-
-
-
-
1.5
5-8
-
MAX
6.0
V
C C
+100
+70
+85
52
3.15
3.47
5.25
3.5
4.60
1.00
0.28
0.40
0.10
2.80
0.37
2.5
-
UNIT
V
V
°C
°C
MHz
V
mA
ELECTRICAL PARAMETERS
∆f/f
25
∆f/f
O
V
C
-
ZV
C
Reference to f
O
, Including 20 years aging
@ +25°C, at time of shipment
[Fmax. - Fmin.]/2, over -40°C to +85°C
±5% change @ +25°C
±5% change
20 years @ +40°C
[Fmax. - Fmin.]/2, over 24 hours
-
V
C
= 1.5V ±1.0V, monotonic positive
-
AC coupled Clipped Sinewave
-
@ 50% Level
-
Pin 8 Logic '1', Output Enabled
Pin 8 Logic '0', Output Disabled [High Imp]
-
± ppm
V
± ppm
kOhm
Vp-p
%
ms
V
dBc/Hz
R
L
// C
L
SYM
T
S
V
IH
V
IL
-
0.8
-
-
10kOhm // 10pF
45
-
0.7*V
C C
-
-
-
-
-
55
2
-
0.3*V
C C
Notes:
0
1 Phase Noise performance may vary based on output frequency. See example plot at 1 MHz below.
.
Document No. 008-0344-0
Page 2 - 3
Rev. B
Model 578
Stratum 3 TCXO/VC-TCXO – Clipped Sine
MECHANICAL SPECIFICATIONS
PACKAGE DRAWING
MARKING INFORMATION
1. M578 – CTS Model Series.
2.
●
– Pin 1 identifier.
3. C – CTS identifier.4.
4. D – Date code. See Table II for codes.
5. xxx – Frequency Code.
Refer to document 016-1454-0, Frequency Code Tables.
NOTES
1. DO NOT make connections to non-labeled pins.
Castellation pins may have internal connections
used in the manufacturing process.
2. Termination pads (e4); barrier plating is nickel
[Ni] with gold [Au] flash plate.
3. Reflow conditions per JEDEC J-STD-020,
260°C maximum.
4. MSL = 1.
SUGGESTED SOLDER PAD GEOMETRY
M578
●
CDXXX
D.U.T. PIN ASSIGNMENTS
PIN
4
5
8
9
10
SYMBOL
GND
Output
EOH
V
CC
V
C
DESCRIPTION
Circuit & Package Ground
Clipped Sine Wave Output
Tri-State Enable
Supply Voltage
Control Voltage – VCTCXO [Note 1]
GND - TCXO
NOTES
1. Connect to ground for TCXO [no AFC] option.
2. DC-Cut Capacitor Required.
Add 1000pF capacitor between TCXO output and input of load.
TEST CIRCUIT – CLIPPED SINE LOAD
TABLE II – DATE CODE
MONTH
YEAR
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
JAN
A
N
a
n
FEB
B
P
b
p
MAR
C
Q
c
q
APR
D
R
d
r
MAY
E
S
e
s
JUN
F
T
f
t
JUL
G
U
g
u
AUG
H
V
h
v
SEP
J
W
j
w
OCT
K
X
k
x
NOV
L
Y
l
y
DEC
M
Z
m
z
Document No. 008-0344-0
Page 3 - 3
Rev. B
FPGA/CPLD
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