162-Ball MCP
MX63UxG
Contents
1. MCP FEATURES ................................................................................................................................3
2. BLOCK DIAGRAM..............................................................................................................................4
3. PART NAME DESCRIPTION ..............................................................................................................5
4. PRODUCT SELECTION GUIDE .........................................................................................................6
5. PIN CONFIGURATIONS .....................................................................................................................7
162-Ball, BGA (NAND x16; LPDDR x32) ............................................................................................................. 7
162-Ball, BGA (NAND x8; LPDDR x32) ............................................................................................................... 8
162-Ball, BGA (NAND x8; LPDDR x16) ............................................................................................................... 9
162-Ball, BGA (NAND x16; LPDDR x16) ........................................................................................................... 10
6. PIN DESCRIPTION ...........................................................................................................................11
LPDDR2 x32 ...................................................................................................................................................... 11
LPDDR2 x16 ...................................................................................................................................................... 12
7. PACKAGE INFORMATION ...............................................................................................................13
8. REVISION HISTORY ........................................................................................................................14
P/N:PM2054
REV. 1.9, October 18, 2016
2
162-Ball MCP
MX63UxG
1. MCP FEATURES
Operation Temperature
•
-30°C to +85°C
•
-40°C to +85°C
Package
• Low Power Dissipation
- Max. 30mA (1.8V)
Active current (Read/Program/Erase)
• Sleep Mode
- 50uA (Max) standby current
• Unique ID Read support (ONFI)
• Secure OTP support
• Electronic Signature (5 Cycles)
• High Reliability
- 8 bit-ECC SLC NAND Flash:
Endurance: typical 100K cycles (with 8-bit ECC
per (512+28) Byte)
- 4 bit-ECC SLC NAND Flash:
Endurance: typical 100K cycles (with 4-bit ECC
per (512+16) Byte)
- Data Retention: 10 years
• 162-ball FBGA - 8.0mmx10.5mm, 1.0mm (h) (max),
0.5mm pitch
NAND Flash Features
•
1G-bit/2G-bit/4G-bit SLC NAND Flash
- Bus: x8 / x16
- 8 bit-ECC SLC NAND Flash:
Page size: (2048+112) byte for x8 bus, (1024+56)
word for x16 bus
Block size: (128K+7K) byte for x8 bus, (64K+2K)
word for x16 bus
- 4 bit-ECC SLC NAND Flash:
Page size: (2048+64) byte for x8 bus, (1024+32)
word for x16 bus
Block size: (128K+4K) byte for x8 bus, (64K+2K)
word for x16 bus
- Plane size:
1024-block/plane x 1 for 1Gb
1024-block/plane x 2 for 2Gb
2048-block/plane x 2 for 4Gb
• ONFI 1.0 compliant
• User Redundancy
- 8 bit-ECC SLC NAND Flash:
112-byte attached to each page
- 4 bit-ECC SLC NAND Flash:
64-byte attached to each page
• Fast Read Access
- Latency of array to register: 25us
- Sequential read: 25ns
• Cache Read Support
• Page Program Operation
- Page program time: 320us (typ.)
• Cache Program Support
• Block Erase Operation
- Block erase time: 1.0ms (typ.)
• Single Voltage Operation:
- VCC: 1.7-1.95V
P/N:PM2054
LPDDR2 DRAM Features
•
•
•
•
JEDEC LPDDR2-S4B compliance
DLL is not implemented
Low power consumption
Mobile RAM functions
- Partial Array Self-Refresh (PASR)
- Auto Temperature Compensated Self-Refresh
(ATCSR) by built-in temperature sensor
- Deep power-down mode
- Per Bank Refresh
• VDD Definition:
Typical
Range
VDD1
1.8V
1.7-1.95V
VDD2
1.2V
1.14-1.3V
VDDQ
1.2V
1.14-1.3V
- Voltage source of VREFCA is VDD2,
VREFCA=1/2*VDD2 (from voltage divider)
- Voltage source of VREFDQ is VDDQ,
VREFDQ=1/2*VDDQ (from voltage divider)
VREFCA
VREFDQ
Min.
0.49xVDD2
0.49xVDDQ
Max.
0.51xVDD2
0.51xVDDQ
REV. 1.9, October 18, 2016
3
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