74HC374; 74HCT374
Rev. 3 — 20 February 2018
Octal D-type flip-flop; positive edge-trigger; 3-state
Product data sheet
1
General description
The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with
3‑state
outputs. The device features a clock (CP) and output enable (OE) inputs. The
flip‑flops
will store the state of their individual D-inputs that meet the set-up and hold
time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes
the outputs to assume a high-impedance OFF-state. Operation of the OE input does not
affect the state of the flip-flops. Inputs also include clamp diodes, this enables the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
The 74HCT374 features reduced input threshold levels to allow interfacing to TTL logic
levels.
2
Features and benefits
•
Input levels:
–
For 74HC374: CMOS level
–
For 74HCT374: TTL level
•
Octal bus interface
•
Non-inverting 3-state outputs
•
8-bit positive, edge-triggered register
•
Common 3-state output enable input
•
Independent register and 3-state buffer operation
•
Complies with JEDEC standard no. 7 A
•
ESD protection:
–
HBM JESD22-A114F exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V
•
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
Octal D-type flip-flop; positive edge-trigger; 3-state
74HC374; 74HCT374
3
Ordering information
Package
Temperature range Name
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1
−40 °C to +125 °C
−40 °C to +125 °C
−40 °C to +125 °C
SO20
SSOP20
TSSOP20
Table 1. Ordering information
Type number
74HC374D
74HCT374D
74HC374DB
74HCT374DB
74HC374PW
74HCT374PW
4
Functional diagram
1
11
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
EN
C1
2
5
6
9
12
15
16
19
mna196
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
FF1
to
FF8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
2
5
6
9
3
4
7
8
13
14
17
18
1D
Q4 12
Q5 15
Q6 16
Q7 19
11 CP
1 OE
mna892
mna891
Figure 1. Logic symbol
D0
D1
Figure 2. IEC logic symbol
D2
D3
D4
Figure 3. Functional diagram
D5
D6
D7
D
CP
Q
FF1
D
CP
FF2
Q
D
CP
Q
FF3
D
CP
Q
FF4
D
CP
FF5
Q
D
CP
FF6
Q
D
CP
Q
FF7
D
CP
FF8
Q
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Figure 4. Logic diagram
74HC_HCT374
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 20 February 2018
2 / 17
Nexperia
Octal D-type flip-flop; positive edge-trigger; 3-state
74HC374; 74HCT374
5
Pinning information
5.1 Pinning
74HC374
74HCT374
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
aaa-028158
74HC374
74HCT374
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
aaa-028159
GND 10
GND 10
Figure 5. Pin configuration SO20
Figure 6. Pin configuration (T)SSOP20
5.2 Pin description
Table 2. Pin description
Symbol
D0, D1, D2, D3, D4, D5, D6, D7
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
OE
CP
GND
V
CC
Pin
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
1
11
10
20
Description
data inputs
data outputs
output enable input (active LOW)
clock pulse input (active rising edge)
ground (0 V)
supply voltage
6
Functional description
[1]
Table 3. Function table
Operating mode
Load and read register
Input
OE
L
L
H
H
CP
↑
↑
↑
↑
Dn
l
h
l
h
Internal
flip-flops
L
H
L
H
Output
Qn
L
H
Z
Z
Load register and disable outputs
[1] H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
74HC_HCT374
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 20 February 2018
3 / 17
Nexperia
Octal D-type flip-flop; positive edge-trigger; 3-state
74HC374; 74HCT374
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO20, SSOP20 and TSSOP20 packages
[1]
Conditions
V
I
< -0.5 V or V
I
> V
CC
+ 0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
-0.5 V < V
O
< V
CC
+ 0.5 V
Min
-0.5
-
-
-
-
-70
-65
-
Max
+7
±20
±20
±35
70
-
+150
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
[1] For SO20 packages: P
tot
derates linearly with 8 mW/K above 70 °C.
For SSOP20 and TSSOP20 packages: P
tot
derates linearly with 5.5 mW/K above 60 °C.
8
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
-
-
-
-40
74HC374
Typ
5.0
-
-
-
1.67
-
+25
Max
6.0
V
CC
V
CC
625
139
83
+125
Min
4.5
0
0
-
-
-
-40
74HCT374
Typ
5.0
-
-
-
1.67
-
+25
Max
5.5
V
CC
V
CC
-
139
-
+125
V
V
V
ns/V
ns/V
ns/V
°C
Unit
Table 5. Recommended operating conditions
Symbol
V
CC
V
I
V
O
Δt/ΔV
T
amb
ambient temperature
74HC_HCT374
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 20 February 2018
4 / 17
Nexperia
Octal D-type flip-flop; positive edge-trigger; 3-state
74HC374; 74HCT374
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
25
Min
74HC374
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
= -20 μA; V
CC
= 2.0 V
I
O
= -20 μA; V
CC
= 4.5 V
I
O
= -20 μA; V
CC
= 6.0 V
I
O
= -6.0 mA; V
CC
= 4.5 V
I
O
= -7.8 mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20 μA; V
CC
= 2.0 V
I
O
= 20 μA; V
CC
= 4.5 V
I
O
= 20 μA; V
CC
= 6.0 V
I
O
= 6.0 mA; V
CC
= 4.5 V
I
O
= 7.8 mA; V
CC
= 6.0 V
I
I
I
OZ
I
CC
C
I
input leakage
current
OFF-state
output current
supply current
input
capacitance
V
I
= V
CC
or GND; V
CC
= 6.0 V
V
I
= V
IH
or V
IL
; V
CC
= 6.0 V;
V
O
= V
CC
or GND
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
-
3.5
0.1
0.1
0.1
0.26
0.26
±0.1
±0.5
8.0
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1.0
±5.0
80
-
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1.0
±10
160
-
V
V
V
V
V
μA
μA
μA
pF
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Typ
Max
T
amb
(°C)
-40 to +85
Min
Max
-40 to +125
Min
Max
Unit
74HC_HCT374
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 20 February 2018
5 / 17
意法半导体-低功耗射频
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
