74LVT2245; 74LVTH2245
Rev. 5 — 10 April 2017
3.3 V octal transceiver with 30 Ω termination resistors; 3-state
Product data sheet
1
General description
The 74LVT2245; 74LVTH2245 is a high-performance BiCMOS product designed for V
CC
operation at 3.3 V.
This device is an octal transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. The device features an output enable input (OE) for easy
cascading and a direction input (DIR) for direction control.
The 74LVT2245; 74LVTH2245 is designed with 30 Ω series resistance in both the HIGH-
state and LOW-state of the output. This design reduces line noise in applications such as
memory address drivers, clock drivers and bus transceivers and transmitters.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
•
30 Ω output termination resistors
Octal bidirectional bus interface
3-state buffers
Output capability: +12 mA and -12 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
–
JESD78: exceeds 500 mA
•
ESD protection:
–
MIL STD 883 method 3015: exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Nexperia
74LVT2245; 74LVTH2245
3.3 V octal transceiver with 30 Ω termination resistors; 3-state
3
Ordering information
Package
Temperature
range
Name
SO20
SSOP20
TSSOP20
Table 1. Ordering information
Type number
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
Version
SOT163-1
SOT339-1
74LVT2245D
74LVTH2245D
74LVT2245DB
74LVTH2245DB
74LVT2245PW
74LVTH2245PW
-40 °C to +85 °C
-40 °C to +85 °C
-40 °C to +85 °C
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
4
Functional diagram
DIR
1
19
A0
A1
A2
A3
A4
A5
A6
A7
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
OE
B0
B1
B2
2
19
1
G3
3 EN1 (BA)
3 EN2 (AB)
V
CC
V
CC
B3
B4
B5
B6
B7
3
4
5
6
7
8
9
1
2
18
17
16
15
14
13
12
11
mna818
mna819
25 Ω
25 Ω
mna817
Figure 1. Logic symbol
Figure 2. IEC logic symbol
Figure 3. Schematic of one output
74LVT_LVTH2245
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 10 April 2017
2 / 15
Nexperia
74LVT2245; 74LVTH2245
3.3 V octal transceiver with 30 Ω termination resistors; 3-state
5
Pinning information
5.1 Pinning
74LVT2245
75LVTH2245
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
aaa-026622
74LVT2245
74LVTH2245
DIR
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
20 V
CC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
001aae465
GND 10
GND 10
Figure 4. Pin configuration for SO20
Figure 5. Pin configuration for SSOP20 and TSSOP20
5.2 Pin description
Table 2. Pin description
Symbol
DIR
A0, A1, A2, A3, A4, A5, A6, A7
GND
B7, B6, B5, B4, B3, B2, B1, B0
OE
V
CC
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11, 12, 13, 14, 15, 16, 17, 18
19
20
Description
direction control input
data input/output
ground (0 V)
data input/output
output enable input
supply voltage
6
Functional description
[1]
Table 3. Function table
Control
OE
L
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Input/output
DIR
L
H
X
An
output An = Bn
input
Z
Bn
input
output Bn = An
Z
74LVT_LVTH2245
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 10 April 2017
3 / 15
Nexperia
74LVT2245; 74LVTH2245
3.3 V octal transceiver with 30 Ω termination resistors; 3-state
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
P
tot
[1]
[2]
[3]
Conditions
[1]
Min
-0.5
-0.5
-0.5
-50
-50
-
-64
-65
[2]
Max
+4.6
+7.0
+7.0
-
-
128
-
+150
150
500
Unit
V
V
V
mA
mA
mA
mA
°C
°C
mW
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
total power dissipation
T
amb
= -40 to +85 °C
[3]
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
-
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which
are detrimental to reliability.
For SO20 package: above 70 °C derate linearly with 8 mW/K.
For (T)SSOP20 package: above 60 °C derate linearly with 5.5 mW/K.
8
Recommended operating conditions
Conditions
Min
2.7
0
-12
-
outputs enabled
in free-air
-
-40
Table 5. Recommended operating conditions
Symbol Parameter
V
CC
V
I
I
OH
I
OL
Δt/ΔV
T
amb
supply voltage
input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
Typ
-
-
-
-
-
+25
Max
3.6
5.5
-
12
10
+85
Unit
V
V
mA
mA
ns/V
°C
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= -40 °C to +85 °C
V
IK
V
IH
V
IL
V
OH
74LVT_LVTH2245
Conditions
V
CC
= 2.7 V; I
IK
= -18 mA
Min Typ
-1.2
2.0
-
[1]
Max Unit
-
-
0.8
-
V
V
V
V
input clamping voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
-0.9
-
-
2.2
V
CC
= 3.0 V; I
OH
= -12 mA
All information provided in this document is subject to legal disclaimers.
2.0
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 10 April 2017
4 / 15
Nexperia
74LVT2245; 74LVTH2245
3.3 V octal transceiver with 30 Ω termination resistors; 3-state
[1]
Symbol Parameter
V
OL
I
I
LOW-level output voltage
input leakage current
Conditions
V
CC
= 3.0 V; I
OL
= 12 mA
control pins
V
CC
= 0 V or 3.6 V; V
I
= 5.5 V
V
CC
= 3.6 V; V
I
= V
CC
or GND
I/O data pins; V
CC
= 3.6 V
V
I
= 5.5 V
V
I
= V
CC
V
I
= 0 V
[2]
Min Typ
-
-
-
-
-
-
-
75
-
[3]
[3]
Max Unit
0.8
10
±1
20
1
-5
-
-75
500
-
125
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
-
1
±0.1
1
0.1
-1
1
150
-150
-
-
60
15
I
OFF
I
BHL
I
BHH
I
BHLO
I
BHHO
I
CEX
I
O(pu/pd)
I
CC
power-off leakage current
bus hold LOW current
bus hold HIGH current
bus hold LOW overdrive current
bus hold HIGH overdrive current
output high leakage current
V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
V
CC
= 3 V; V
I
= 0.8 V
V
CC
= 3 V; V
I
= 2.0 V
V
CC
= 0 V to 3.6 V; V
I
= 3.6 V
V
CC
= 0 V to 3.6 V; V
I
= 3.6 V
output in HIGH-state when V
O
> V
CC
;
V
O
= 5.5 V; V
CC
= 3.0 V
[4]
±100 μA
-
-500
-
-
power-up/power-down output current V
CC
≤ 1.2 V; V
O
= 0.5 V to V
CC
;
V
I
= GND or V
CC
; OE = don’t care
supply current
V
CC
= 3.6 V; V
I
= GND or V
CC
; I
O
= 0 A
outputs HIGH
outputs LOW
outputs disabled
±100 μA
-
-
[5]
[6]
0.13
3
0.13
0.1
0.19
12
0.19
0.2
mA
mA
mA
mA
-
-
ΔI
CC
additional supply current
per input pin; V
CC
= 3 V to 3.6 V;
one input at V
CC
- 0.6 V; other inputs at
V
CC
or GND
DIR and OE; V
I
= 0 V or 3.0 V
An and Bn; outputs disabled;
V
I/O
= 0 V or 3.0 V
C
I
C
I/O
input capacitance
input/output capacitance
-
-
4
10
-
-
pF
pF
[1]
[2]
[3]
[4]
[5]
[6]
Typical values are measured at V
CC
= 3.3 V and T
amb
= 25 °C.
Unused pins at V
CC
or GND.
This is the bus hold overdrive current required to force the input to the opposite logic state.
This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 ms. From V
CC
= 1.2 V to V
CC
= 3.0 V to 3.6 V a transition time
of 100 μs is permitted.
I
CC
is measured with outputs pulled to V
CC
or GND.
This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
74LVT_LVTH2245
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 10 April 2017
5 / 15
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