DEMO MANUAL DC1367A
LTM4615EV:
Dual DC/DC Step-Down
µModule Regulator with LDO
DESCRIPTION
Demonstration circuit 1367A features the LTM
®
4615EV, a
triple output μModule
®
regulator consisting of two switch
mode outputs and one LDO output. Each LTM4615 DC/DC
converter has a separate input and enable pin. The LTM4615
maximum load current is 4A for each switch mode channel
and 1.5A for the VLDO™ channel. However the DC1367A
is configured with the LDO input supply connected to
the VOUT2 whose maximum output current decreases
accordingly. Derating is necessary for certain V
IN
, V
OUT
and thermal conditions. The LTM4615 data sheet must be
read in conjunction with this manual prior to working on
or modifying DC1367A.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, μModule, Linear Technology and the Linear logo are registered trademarks
and VLDO is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
PERFORMANCE SUMMARY
PARAMETER
Input Voltage Range
Output Voltage V
OUT1
Output Voltage V
OUT2
Output Voltage V
O3(LDO)
Maximum Continuous Output Current
Default Operating Frequency
Efficiency of Channel 1
Efficiency of Channel 2
(T
A
= 25°C)
VALUE
2.5V to 5.5V
1.8V ±2%
1.2V ±2%
1.0V ±2%
4A DC at V
OUT1
, 4A DC at V
OUT2
, 1.5A DC at V
O3
1.25MHz
82.8%, See Figure 3
81.7%, See Figure 3
CONDITION
Both Switch Mode Outputs (V
IN1
and V
IN2
)
DC Voltage, V
IN1
= 3.3V, I
OUT1
= 4A
DC Voltage, V
IN2
= 3.3V, I
OUT2
= 2.5A
DC Voltage, V
IN2
= 3.3V, I
OUT3
= 1.5A
Note: I
OUT2
= 4.0A – I
03
For 2 Switching Mode Channels
V
IN1
= 5.5V, V
OUT1
= 1.8V, I
OUT1
= 4A
V
IN2
= 5.5V, V
OUT2
= 1.2V, I
OUT2
= 2.5A
BOARD PHOTO
dc1367af
1
DEMO MANUAL DC1367A
QUICK START PROCEDURE
Demonstration circuit 1367A is an easy way to evaluate
the performance of the LTM4615. Please refer to Figure 1
for proper measurement equipment setup and follow the
procedure below:
1. Place jumpers in the following positions for a typical
1.8V, 1.2V and 1.0V application:
TRACK1
DISABLED
RUN1
ON
RUN2
ON
4. Once the proper output voltage is established, adjust
the load within the operating range and observe the
output voltage regulation, ripple voltage, efficiency and
other parameters. To measure input and output ripple,
please refer to Figure 2 for proper setup.
5. VOUT1 can track another supply by connecting TP14,
TRACK to the supply rail and setting JP1 to ENABLED.
When R8 equals RSET1, VOUT1 is set up for coincidental
tracking. VOUT2 is set up to coincidentally track VOUT1
as determined by resistors R6 and R7. Please refer to
the circuit schematic and data sheet.
6. VOUT2 is used as the input supply for the 1.5A LDO.
Therefore, if the jumper of JP3 (RUN2) is placed at OFF
position, both channel 2 and 3 will be turned off.
7. Because DC1367A is designed so VOUT2 tracks VOUT1
automatically, placing the JP2 (RUN1) to OFF position
turns off all three outputs. To disable tracking on VOUT2,
please remove R6 and R7 and connect TRACK2 to VIN2.
8. VIN1 and VIN2 are shorted on DC1367A through a 1mΩ
resistor, R10. If desired, remove R10 to allow separate
V
IN1
and V
IN2
power supplies.
2. With power off, preset the loads to 0A and V
IN
supply
to be 5V. Connect the input power supply, load and
meters as shown in Figure 1.
3. Turn on the power at the input. The output voltage
between VO1+ and VO1– should be 1.8V ± 2%, the
voltage between VO2+ and VO2– should be 1.2V ± 2%,
and the voltage between VO3(LDO) and GND should be
1.0V ±2%.
+
–
V
–
A
LOAD
0A TO
1.5A
+
–
+
V
LOAD
0A TO
4A
A
+
+
A
–
LOAD
0A TO
2.5A
+
V
–
–
–
V
IN
A
DC1376 F01
+
+
–
DC1376 F02
–
V
Figure 1. Test Setup of DC1367A
2
+
+
–
INPUT OR OUTPUT CAPACITOR
Figure 2. Proper Scope Probe Placement for Measuring
Input or Output Ripple
dc1367af
DEMO MANUAL DC1367A
QUICK START PROCEDURE
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
EFFICIENCY (%)
V
IN1
= 5.5V, V
OUT 1
= 1.8V
CHANNEL 2 AND 3 OFF
V
IN2
= 5.5V, V
OUT 2
= 1.2V
CHANNEL 1 AND 3 OFF
V
IN3
= 1.2V, V
OUT 3
= 1.0V
CHANNEL 1 AND 2 OFF
0
0.5
1.0
1.5 2.0 2.5 3.0
LOAD CURRENT (A)
3.5
4.0
DC1376 F03
Figure 3. Measured Efficiency for Different Channels
V
OUT1
50mV/DIV
I
OUT1
2A/DIV
DC1367 F04
V
IN1
= 5.5V
20μs/DIV
V
OUT1
= 1.8V
V
OUT2
= 1.2V AT NO LOAD
V
O3(LDO)
= 1.0V AT NO LOAD
CONTINUOUS CURRENT MODE (CCM)
0A TO 3.4A LOAD STEP ON V
OUT1
C
OUT1
= 100μF CERAMIC (1210, X5R, 6.3V) + 22μF CERAMIC (1206, X5R, 6.3V)
Figure 4. Measured Load Transient Response for V
OUT1
V
OUT2
20mV/DIV
I
OUT2
1A/DIV
DC1367 F05
V
IN2
= 5.5V
20μs/DIV
V
OUT2
= 1.2V
V
OUT1
= 1.8V AT NO LOAD
V
O3(LDO)
= 1.0V AT NO LOAD
CONTINUOUS CURRENT MODE (CCM)
0A TO 2.2A LOAD STEP ON V
OUT2
C
OUT2
= 100μF CERAMIC (1210, X5R, 6.3V) + 22μF CERAMIC (1206, X5R, 6.3V)
Figure 5. Measured Load Transient Response for V
OUT2
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3
DEMO MANUAL DC1367A
PARTS LIST
ITEM
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
1
2
3
4
5
QTY
2
2
2
5
1
1
1
2
1
3
1
1
0
0
0
0
0
1
1
3
3
7
14
4
REFERENCE
CIN6, CIN10
CO4, CO9
CO3, CO8
C1, CIN3, CIN4, CIN8, CIN9
CIN5
L1
RSET1
RSET2, R7
RSET3
R1,R2, R9
R6
U1
CO1, CO6 (OPT)
CSS1, CSS2, CP1, CP2, C3, C4 (OPT)
COMP1, COMP2, CFF1, CFF2 (OPT)
CO5, CO7, CO10, CO2(OPT)
R8
R5
R10
JP1, JP2, JP3
JP1, JP2, JP3
TP8-TP11, TP22, TP2, TP3
TP1, TP4-TP7, TP12-TP18, TP21, TP23
STAND OFF
PART DESCRIPTION
CAP OS-CON, 47μF 10V, C6 SIZE
.,
,
CAP X5R, 100μF 6.3V, 10%,1210-7343
.,
,
CAP X5R, 22μF 6.3V, 20%, 1206-0805
.,
,
CAP X5R, 10μF 6.3V, 20%, 1206-0805
.,
,
CAP X5R, 10μF 6.3V, 20%, 0805-0603
.,
,
IND, 0.2μH
RES., CHIP 4.02k, 1/16W, 1%, 0603
,
RES., CHIP 10k, 1/16W, 1%, 0603
,
RES., CHIP 3.32k, 1/16W, 1%, 0603
,
RES., CHIP 100k, 1/16W, 1%, 0603
,
RES., CHIP 4.99k, 1/16W, 1%, 0603
,
I.C., LTM4615EV#PBF LGA
,
CAP 1206-0805
.,
CAP 0603
.,
CAP 0603
.,
CAP 1210-7343
.,
RES., CHIP 0603
,
RES., CHIP 4.99k, 1/16W, 1%, 0603
,
RES., CHIP 1M, 1W, 1%, 2512
,
2MM SINGLE ROW HEADER, 3 PIN
SHUNT,
BANANA JACK,
TESTPOINT, TURRET, .095”
STAND-OFF NYLON 0.50” tall
,
VISHAY, CRCW06034K99FKEA
PANASONIC, ERJM1WTJ1M0U
SAMTEC, TMM-103-02-L-S
SAMTEC, 2SN-BK-G
KEYSTONE, 575-4
MILL-MAX, 2501-2-00-80-00-00-07-0
KEYSTONE, 8833 (SNAP ON)
MANUFACTURER/PART NUMBER
SANYO, 10SVP47M
AVX, 12106D107KAT2A
AVX, 12066D226MAT2A
AVX, 12066D106MAT2A
AVX, 08056D106MAT2A
Fair-Rite, 2508056017Y2
VISHAY, CRCW06034K02FKEA
VISHAY, CRCW060310K0FKEA
VISHAY, CRCW060333K2FKEA
VISHAY, CRCW0603100KFKEA
VISHAY, CRCW06034K99FKEA
LINEAR TECH., LTM4615EV#PBF
Required Circuit Components
Additional Demo Board Circuit Components
Hardware For Demo Board Only
dc1367af
4
A
B
TP21
R10
TP22
VIN1
+
J1
J2
J3
J4
J5
K1
K2
K3
K4
K5
H2
H3
H4
H5
H6
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
VIN2+
VIN1+
SW1
VIN2
CIN10
47uF
CIN9
10uF
R2
100K
CIN8
10uF
TP23
GND
SW2
0.001
VIN2
2.5V - 5.5V
TP1
VIN1
2.5V - 5.5V
CIN6
47uF
SW1
SW1
SW1
SW1
SW1
VIN1
VIN1
VIN1
VIN1
VIN1
VIN1
VIN1
VIN1
VIN1
VIN1
SW2
SW2
SW2
SW2
SW2
L4
PGOOD1
VIN2
VIN2
VIN2
VIN2
VIN2
VIN2
VIN2
VIN2
VIN2
VIN2
VIN2
TP2
R1
100K
GND
+
TP3
CIN3
10uF
6.3V
CIN4
10uF
6.3V
GND
TP4
PGOOD1
PGOOD2
E4
TP17
PGOOD2
TP5
SCHEMATIC DIAGRAM
A
VOUT1
VOUT2
VO1+
CO2
(OPT)
CO6
(OPT)
CO7
(OPT)
CO8
22uF
6.3V
CO9
100uF
6.3V
CO3
22uF
6.3V
CO4
100uF
6.3V
CO5
(OPT)
TP6
TP8
CO10
(OPT)
TP10
RSET2 10K 1%
CP2
E5
VO2+
A
TP7
CO1
(OPT)
VOUT1
1.8V@4A
MAX
L5
COMP1
TP9
K9
K10
K11
K12
L9
L10
L11
L12
M9
M10
M11
M12
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT1
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
VOUT2
FB2
FB1
E6
C9
C10
C11
C12
D9
D10
D11
D12
E11
E12
VOUT2
1.2V@2.5A
MAX
GND
TP12
(OPT)
VO2-
GND
CCOMP1
(OPT)
U1
LTM4615EV
COMP2
TRACK1
EN3
RUN/SS1
F8
L6
L3
TP11
VO1-
TP13
RSET1 4.02K 1%
L2
CFF2
L1
CIN5
10uF
6.3V
0.2uH
CCOMP2
(OPT)
(OPT)
VOUT2
CP1 (OPT)
CFF1
VIN1
1
(OPT)
JP1
TRACK1
2
LDO_OUT
LDO_OUT
LDO_OUT
LDO_OUT
FB3
F6
G9
G10
G11
G12
VOUT1
LDO_IN
LDO_IN
LDO_IN
LDO_IN
G1
G2
G3
G4
DISABLED
ENABLED
3
1
F1
F2
F3
F4
F5
F7
F9
F10
F11
F12
G6
G7
G8
GND3
GND3
GND3
GND3
GND3
GND3
GND3
GND3
GND3
GND3
GND3
GND3
GND3
TRACK
ON
2
G5
PGOOD3
BOOST3
RUN/SS2
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND1
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
GND2
TRACK2
R5
4.99K
JP2
RUN1
E3
E7
TP14
OFF
3
R8
(OPT)
CSS1
(OPT)
RSET3
3.32K
C1
10uF
6.3V
C3
(OPT)
TP15
VO3 (LDO)
1V@1.5A
MAX
TP16
E2
GND
C4
(OPT)
VIN2
1
VOUT1
R6
4.99K 1%
JP3
2
H1
H7
H8
H9
H10
H11
H12
J6
J7
J8
J9
J10
J11
J12
K6
K7
K8
L1
L7
L8
M1
M2
M3
M4
M5
M6
M7
M8
R9
VOUT1
100K
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B7
B8
B9
B10
B11
B12
C7
C8
D6
D7
D8
E1
E8
E9
E10
PGOOD3
TP18
R7
10K 1%
CSS2
(OPT)
3
B
B
CONTRACT NO.
APPROVALS
DRAWN
CHECKED
APPROVED
ENGINEER
DESIGNER
Judy Sun
11/28/07
HELEN
DATE
11/28/07
TECHNOLOGY
TITLE
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
LTM4615EV High Density
Dual Output Step-Down Power uModule with VLDO
SIZE
CAGE CODE
DWG NO
DC1367A
Thursday, July 24, 2008
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