LTC5800-IPM
SmartMesh IP Node 2.4GHz
802.15.4e Wireless Mote-on-Chip
neTwork FeaTures
n
DescripTion
SmartMesh IP™ wireless sensor networks are self manag-
ing, low power internet protocol (IP) networks built from
wireless nodes called motes. The
LTC
®
5800-IPM
is the
IP mote product in the Eterna
®
* family of IEEE 802.15.4e
System-on-Chip (SoC) solutions, featuring a highly-
integrated, low power radio design by Dust Networks
®
as
well as an ARM Cortex-M3 32-bit microprocessor running
Dust’s embedded SmartMesh IP networking software.
The LTC5800-IPM SoC features an on-chip power ampli-
fier (PA) and transceiver, requiring only power supply
decoupling, crystals, and antenna with matching circuitry
to create a complete wireless node.
With Dust’s time-synchronized SmartMesh IP networks,
all motes in the network may route, source or terminate
data, while providing many years of battery powered
operation. The SmartMesh IP software provided with the
LTC5800-IPM is fully tested and validated, and is read-
ily configured via a software Application Programming
Interface.
SmartMesh IP motes deliver a highly flexible network
with proven reliability and low power performance in an
easy-to-integrate platform.
L,
LT, LTC, LTM, Linear Technology, the Linear logo, Dust, Dust Networks, SmartMesh and
Eterna are registered trademarks and LTP, the Dust Networks logo, SmartMesh IP and Mote-
on-Chip are trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217,
7791419, 7881239, 7898322, 8222965.
* Eterna is Dust Networks’ low power radio SoC architecture.
n
n
n
Complete Radio Transceiver, Embedded Processor,
and Networking Software for Forming a Self-Healing
Mesh Network
SmartMesh
®
Networks Incorporate:
n
Time Synchronized Network-Wide Scheduling
n
Per Transmission Frequency Hopping
n
Redundant Spatially Diverse Topologies
n
Network-Wide Reliability and Power Optimization
n
NIST Certified Security
SmartMesh Networks Deliver
n
>99.999% Network Reliability Achieved in the
Most Challenging RF Environments
n
Sub 50µA Routing Nodes
Compliant to 6LoWPAN Internet Protocol (IP) and
IEEE 802.15.4e Standards
lTc5800-ipM FeaTures
n
n
n
n
n
Industry-Leading Low Power Radio Technology
n
4.5mA to Receive a Packet
n
9.7mA to Transmit at 8dBm
PCB Module Versions Available (LTP5901/
LTP5902-IPM) with RF Modular Certifications
2.4GHz, IEEE 802.15.4e System-on-Chip
72-Pin 10mm × 10mm QFN Package
Micrium µCOS-II Real Time Operating System based
On-Chip Software Development Kit
Typical applicaTion
20MHz
20MHz
LTC5800-IPM
ANTENNA
IN+
SENSOR
IN–
LTC2379-18 SPI
µCONTROLLER
UART
LTC5800-IPR
ANTENNA
UART
HOST
APPLICATION
32kHz
32kHz
5800IPM TA01
5800ipmfa
For more information
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1
LTC5800-IPM
Table oF conTenTs
Network Features .......................................... 1
LTC5800-IPM Features .................................... 1
Typical Application ........................................ 1
Description.................................................. 1
SmartMesh Network Overview........................... 3
Absolute Maximum Ratings .............................. 4
Order Information .......................................... 4
Pin Configuration .......................................... 4
Recommended Operating Conditions ................... 5
DC Characteristics ......................................... 5
Radio Specifications ...................................... 5
Radio Receiver Characteristics .......................... 6
Radio Transmitter Characteristics ....................... 6
Digital I/O Characteristics ................................ 7
Temperature Sensor Characteristics .................... 7
Analog Input Chain Characteristics ..................... 7
System Characteristics ................................... 8
UART AC Characteristics.................................. 8
TIMEn AC Characteristics ................................. 9
Radio_Inhibit AC Characteristics ....................... 10
Flash AC Characteristics ................................. 10
Flash SPI Slave AC Characteristics .................... 11
SPI Master AC Characteristics .......................... 12
I
2
C AC Characteristics .................................... 13
Typical Performance Characteristics .................. 15
Pin Functions .............................................. 20
Operation................................................... 26
Power Supply..........................................................26
Supply Monitoring and Reset ................................. 27
Precision Timing ..................................................... 27
Application Time Synchronization .......................... 27
Time References ..................................................... 27
Radio ...................................................................... 28
UARTs ..................................................................... 28
Autonomous MAC...................................................29
Security ..................................................................29
Temperature Sensor ...............................................30
Radio Inhibit ...........................................................30
Flash Programming ................................................30
FLASH Data Retention ............................................30
State Diagram .........................................................30
SPI Master .............................................................. 32
I
2
C Master ..............................................................33
1-Wire Master .........................................................33
Applications Information ................................ 33
Modes of Operation ................................................33
Slave Mode .............................................................33
Master Mode ..........................................................33
On-Chip SDK (OCSDK) ...........................................33
Regulatory and Standards Compliance ...................34
Soldering Information .............................................34
Related Documentation .................................. 35
Package Description ..................................... 36
Revision History .......................................... 37
Typical Application ....................................... 38
Related Parts .............................................. 38
2
5800ipmfa
For more information
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LTC5800-IPM
sMarTMesh neTwork overview
A SmartMesh network consists of a self-forming multi-hop
mesh of nodes, known as motes, which collect and relay
data, and a network manager that monitors and manages
network performance and security, and exchanges data
with a host application.
SmartMesh networks communicate using a time slotted
channel hopping (TSCH) link layer, pioneered by Dust
Networks. In a TSCH network, all motes in the network
are synchronized to within less than a millisecond. Time
in the network is organized into time slots, which enables
collision-free packet exchange and per-transmission
channel-hopping. In a SmartMesh network, every device
has one or more parents (e.g. mote 3 has motes 1 and
2 as parents) that provide redundant paths to overcome
communications interruption due to interference, physical
obstruction or multi-path fading. If a packet transmission
fails on one path, the next retransmission may try on a
different path and different RF channel.
A network begins to form when the network manager
instructs its on-board Access Point (AP) radio to begin
sending advertisements—packets that contain information
that enables a device to synchronize to the network and
request to join. This message exchange is part of the secu-
rity handshake that establishes encrypted communications
between the manager or application, and mote. Once motes
have joined the network, they maintain synchronization
through time corrections when a packet is acknowledged.
HOST
APPLICATION
The Network Manager uses health reports to continually
optimize the network to maintain >99.999% data reliability
even in the most challenging RF environments.
The use of TSCH allows SmartMesh devices to sleep in
between scheduled communications and draw very little
power in this state. Motes are only active in time slots
where they are scheduled to transmit or receive, typically
resulting in a duty cycle of < 1%. The optimization soft-
ware in the Network Manager coordinates this schedule
automatically. When combined with the Eterna low power
radio, every mote in a SmartMesh network—even busy
routing ones—can run on batteries for years. By default,
all motes in a network are capable of routing traffic from
other motes, which simplifies installation by avoiding the
complexity of having distinct routers vs non-routing end
nodes. Motes may be configured as non-routing to further
reduce that particular mote’s power consumption and to
support a wide variety of network topologies.
ALL NODES ARE ROUTERS.
THEY CAN TRANSMIT AND RECEIVE.
THIS NEW NODE CAN JOIN
ANYWHERE BECAUSE ALL
NODES CAN ROUTE.
SNO 02
NETWORK MANAGER
AP
Mote
1
Mote
2
Mote
3
SNO 01
An ongoing discovery process ensures that the network
continually discovers new paths as the RF conditions
change. In addition, each mote in the network tracks per-
formance statistics (e.g. quality of used paths, and lists of
potential paths) and periodically sends that information
to the network manager in packets called health reports.
At the heart of SmartMesh motes and network manag-
ers is the Eterna IEEE 802.15.4e System-on-Chip (SoC),
featuring Dust Networks’ highly integrated, low power
radio design, plus an ARM Cortex-M3 32-bit micropro-
cessor running SmartMesh networking software. The
SmartMesh networking software comes fully compiled
yet is configurable via a rich set of Application Program-
ming Interfaces (APIs) which allows a host application
to interact with the network, e.g. to transfer information
to a device, to configure data publishing rates on one or
more motes, or to monitor network state or performance
metrics. Data publishing can be uniform or different for
each device, with motes being able to publish infrequently
or faster than once per second as needed.
5800ipmfa
For more information
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3
LTC5800-IPM
absoluTe MaxiMuM raTings
(Note 1)
pin conFiguraTion
Pin functions shown in italics are currently not supported in software.
TOP VIEW
72 TIMEn
71 UART_TX
70 UART_TX_CTSn
69 UART_TX_RTSn
68 UART_RX
67 UART_RX_CTSn
66 UART_RX_RTSn
65 VSUPPLY
64 CAP_PRIME_1P
63 CAP_PRIME_1M
62 CAP_PRIME_2M
61 CAP_PRIME_2P
60 CAP_PRIME_3P
59 CAP_PRIME_3M
58 CAP_PRIME_4M
57 CAP_PRIME_4P
56 VPRIME
55 FLASH_P_ENn
RADIO_INHIBIT 1
CAP_PA_1P 2
CAP_PA_1M 3
CAP_PA_2M 4
CAP_PA_2P 5
CAP_PA_3P 6
CAP_PA_3M 7
CAP_PA_4M 8
CAP_PA_4P 9
VDDPA 10
LNA_EN /
GPIO17
11
RADIO_TX /
GPIO18
12
RADIO_TXn /
GPIO19
13
ANTENNA 14
AI_0 15
AI_1 16
AI_3 17
AI_2 18
Supply Voltage on VSUPPLY ..................................4.20V
Input Voltage on AI_0/1/2/3 Inputs ........................1.80V
Voltage on Any Digital I/O Pin ...–0.3V to V
SUPPLY
+ 0.3V
Input RF Level ......................................................10dBm
Storage Temperature Range (Note 3)..... –55°C to 125°C
Junction Temperature (Note 3) ............................. 125°C
Operating Temperature Range
LTC5800I .............................................–40°C to 85°C
LTC5800H .......................................... –55°C to 105°C
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions
be observed when handling the LTC5800-IPM.
EXPOSED PAD
(GND)
54 VPP
53
SPIS_SSn
/ SDA
52
SPIS_SCK
/ SCL
51
SPIS_MOSI
/ GPIO26 /
UARTC1_RX
50
SPIS_MISO
/ 1_WIRE /
UARTC1_TX
49
PWM0
/ GPIO16
48 DP1 (GPIO20) /
TIMER16_IN
47 SPIM_SS_0n / GPIO12
46 SPIM_SS_1n / GPIO13
45 IPCS_SSn / GPIO3
44 IPCS_SCK / GPIO4
43 SPIM_SCK / GPIO9
42 IPCS_MOSI / GPIO5
41 SPIM_MOSI / GPIO10
40 IPCS_MISO / GPIO6
39 SPIM_MISO / GPIO11
38 UARTCO_RX
37 UARTCO_TX
T
JMAX
= 125°C,
θ
JA
= 21°C/W,
θ
JCbottom
= 0.6°C/W
EXPOSED PAD IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC5800IWR-IPMA#PBF
TAPE AND REEL
LTC5800IWR-IPMA#PBF
PART MARKING*
LTC5800WR-IPMA
PACKAGE DESCRIPTION
72-Lead (10mm × 10mm × 0.85mm) Plastic QFN
72-Lead (10mm × 10mm × 0.85mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 85°C
–55°C to 105°C
LTC5800HWR-IPMA#PBF LTC5800HWR-IPMA#PBF LTC5800WR-IPMA
*The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to:
http://www.linear.com/packaging/.
Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
OSC_32K_XOUT 19
OSC_32K_XIN 20
VBGAP 21
RESETn 22
TDI 23
TDO 24
TMS 25
TCK 26
DP4 (GPIO23) 27
OSC_20M_XIN 28
OSC_20M_XOUT 29
VDDA 30
VCORE 31
VOSC 32
DP3 (GPIO22) /
TIMER8_IN
33
DP2 (GPIO21) /
LPTIMER_IN
34
SLEEPn
/
GPIO14
35
DP0 (GPIO0) / SPIM_SS_2n 36
WR PACKAGE
72-LEAD PLASTIC QFN
4
5800ipmfa
For more information
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LTC5800-IPM
The
l
denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at T
A
= 25°C and V
SUPPLY
= 3.6V unless otherwise noted.
SYMBOL
V
SUPPLY
PARAMETER
Supply Voltage
Supply Noise
Operating Relative Humidity
Temperature Ramp Rate
CONDITIONS
Including Noise and Load Regulation
Requires Recommended RLC Filter, 50Hz to 2MHz
Non-condensing
While Operating in Network
l
l
l
l
recoMMenDeD operaTing conDiTions
MIN
2.1
10
–8
TYP
MAX
3.76
250
90
+8
UNITS
V
mV
% RH
°C/min
Dc characTerisTics
OPERATION/STATE
Reset
Power-on Reset
Doze
Deep Sleep
In-Circuit Programming
Peak Operating Current
+8dBm
+0dBm
Active
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C and V
SUPPLY
= 3.6V unless otherwise noted.
CONDITIONS
After Power-on Reset
During Power-on Reset, Maximum 750µs + VSUPPLY Rise Time
from 1V to 1.9V
RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All
Data and State Retained, 32.768kHz Reference Active
RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All
Data and State Retained, 32.768kHz Reference Inactive
RESETn and FLASH_P_ENn Asserted, IPCS_SCK @ 8MHz
System Operating at 14.7MHz, Radio Transmitting, During Flash
Write. Maximum duration 4.33 ms.
ARM Cortex M3, RAM and Flash Operating, Radio and All Other
Peripherals Off. Clock Frequency of CPU and Peripherals Set to
7.3728MHz, VCORE = 1.2V
Single Bank Flash Write
Single Bank Page or Mass Erase
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
MIN
TYP
1.2
12
1.2
0.8
20
30
26
1.3
MAX
UNITS
µA
mA
µA
µA
mA
mA
mA
mA
Flash Write
Flash Erase
Radio Tx
+0dBm (LTC5800I)
+0dBm (LTC5800H)
+8dBm (LTC5800I)
+8dBm (LTC5800H)
Radio Rx
LTC5800I
LTC5800H
3.7
2.5
5.4
5.6
9.7
9.9
4.5
4.7
mA
mA
mA
mA
mA
mA
mA
mA
Current With Autonomous MAC Managing Radio Operation,
CPU Inactive. Clock Frequency of CPU and Peripherals Set to
7.3728MHz.
raDio speciFicaTions
PARAMETER
Frequency Band
Number of Channels
Channel Separation
Channel Center Frequency
Raw Data Rate
Antenna Pin ESD Protection
Range (Note 4)
Indoor
Outdoor
Free Space
CONDITIONS
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C and V
SUPPLY
= 3.6V unless otherwise noted.
MIN
l
l
l
TYP
15
5
2405 + 5•(k-11)
250
±1000
100
300
1200
MAX
2.4835
UNITS
GHz
MHz
MHz
kbps
V
m
m
m
5800ipmfa
2.4000
Where k = 11 to 25, as Defined by IEEE.802.15.4
HBM Per JEDEC JESD22-A114F
25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m
Above Ground
l
l
For more information
www.linear.com/LTC5800-IPM
5
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