MUSES72320
±18V Operation 2-Channel Electronic Volume
s
GENERAL DESCRIPTION
The
MUSES72320
is a ±18V operation 2-channel
electronic volume, which is optimized for high-end audio
and professional audio applications with advanced circuitry
and layout. The
MUSES72320
performs low noise and low
distortion characteristics and with resistance ladder circuit.
All of functions are controlled via three-wired serial bus.
Selectable 8-Chip address is available for using four chips
on same serial bus line.
It’s suitable for highly linear volume control of Hi-fi audio
systems.
s
PACKAGE OUTLINE
MUSES72320V
s
FEATURES
q
Operating Voltage
q
3-Wired Serial Control
q
Selectable 8-Chip Address
q
Low Output Noise
q
Low Distortion
q
Volume
q
q
q
q
±8.5 to ±18V
Chip Address Select Function
Available for using eight chips on same serial bus line
*It conforms to the characteristic of an external operational amplifier.
*It conforms to the characteristic of an external operational amplifier.
0dB to –111.5dB /0.25dBstep, MUTE
+31.5 to 0dB / 0.5dBstep
Channel Separation
-120dB typ.
Zero Cross Detection circuit Detection
CMOS Technology
Package Outline
SSOP32
s
BLOCK DIAGRAM
InA
InB
V
+
Zero Cross Detection
Z/ C
D_VDD
+5V
D_REF
Control Logic
V-
DATA LATCH ADR0 ADR2
CLOCK
ADR1
Ver. 0.6E
–1–
MUSES72320
s
PIN FUNCTION
32
17
1
16
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SYMBOL
Z/C REFL
L_REF
L+
L_REF
L-
L_REF
OutL
FUNCTION
Lch Zero Cross Detection circuit
Reference Voltage
Lch Reference Voltage
Lch Opamp non-inverting input
connect terminal
Lch Reference Voltage
Lch Opamp inverting input connect
terminal
Lch Reference Voltage
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SYMBOL
D_VDD
DATA
CLOCK
LATCH
D_REF
V+
InR
V+
V-
InL
V-
D_CAP
ADR2
ADR1
ADR0
Z/C
FUNCTION
Digital block Power Supply
Control data signal input
Clock signal input
Latch signal input
Digital block Reference Voltage
Power Supply (+)
Rch input
Power Supply (+)
Power Supply (-)
Lch input
Power Supply (-)
Digital block Noise Rejection
Capacitor terminal
Chip address setting terminal 2
Chip address setting terminal 1
Chip address setting terminal 0
Zero Cross Detection circuit ON/OFF
setting terminal
Lch output
Switching noise rejection capacitor
DCCAP_L
(Lch)
Switching noise rejection capacitor
DCCAP_R
(Rch)
OutR
Rch output
R_REF
R-
R_REF
R+
R_REF
Z/C REFR
Rch Reference Voltage
Rch Opamp inverting input connect
terminal
Rch Reference Voltage
Rch Opamp non-inverting input
connect terminal
Rch Reference Voltage
Rch Zero Cross Detection circuit
Reference Voltage
–2–
Ver. 0.6E
MUSES72320
s
ABSOLUTE MAXIMUM RATING (Ta=25°C)
°
PARAMETER
SYMBOL
Power Supply Voltage
Maximum Input Voltage
Power Dissipation
Operating Temperature Range
Storage Temperature Range
V
+
/V
-
V
IM
P
D
Topr
Tstg
RATING
+20/-20
V
+
/V
-
1000
NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting
UNIT
V
V
mW
°C
°C
-40 ~ +85
-40 ~ +125
s
ELECTRICAL CHARACTERISTICS
PARAMETER
x
Power Supply
Operating Voltage
Supply Current 1
Supply Current 2
SYMBOL
+
-
TEST CONDITION
MIN.
±8.5
TYP.
±15.0
2.0
2.0
MAX.
±18.0
10.0
10.0
UNIT
(Ta=25°C, V /V =±15V, unless otherwise specified)
V
+
/V
-
I
CC
I
EE
No signal
No signal
V
mA
mA
-
-
x
Input/Output Characteristics1 (Output)
(Ta=25°C,V
+
/V
-
=±15V, V
IN
=2Vrms, f=1kHz, Volume=0dB, Gain=0dB, V
OUT
with MUSES01, R
L
=47kΩ, unless otherwise specified)
Maximum Input Voltage
Voltage Gain 1
Voltage Gain 2
Voltage Gain Error 1
Voltage Gain Error 2
Maximum Attenuation
Mute level
Channel Separation 1
Channel Separation 2
Input Impedance
V
IM
G
V1
G
V2
∆G
V1
∆G
V2
A
TT
Mute
CS1
CS2
R
IN
f=1kHz,THD=1%
Volume=-20dB
V
IN
=2Vrms, f=1kHz
Volume=0dB
V
IN
=200mVrms, f=1kHz
Volume=+15dB
V
IN
=2Vrms, f=1kHz
Volume=0dB
V
IN
=2Vrms, f=1kHz
Volume=-60dB
V
IN
=4Vrms, f=1kHz
Volume=-111.5dB, A-weight
f=1kHz, V
IN
=4Vrms
Volume=Mute, A-weight
f=1kHz, V
IN
=2Vrms,A-weight
Volume=0dB, Rg=0Ω
f=20kHz, V
IN
=2Vrms
Volume=0dB, Rg=0Ω
23pin, 26pin
10.9
-0.5
+14
-0.5
-1.0
-
-
-
-
14
-
0
+15
0
0
-111.5
-120
-110
-90
20
-
0.5
+16
0.5
1.0
-
-
-90
-
-
Vrms
dB
dB
dB
dB
dB
dB
dB
dB
kΩ
x
Input/Output Characteristics2 (Output)
(Ta=25°C,V
+
/V
-
=±15V, V
IN
=2Vrms, f=1kHz, Volume=0dB, Gain=0dB, V
OUT
with MUSES01, R
L
=47kΩ, unless otherwise specified)
Maximum Output Voltage
Total Harmonic Distortion 1
Total Harmonic Distortion 2
V
OM
THD1
THD2
f=1kHz,THD=1%
Volume=-6dB, Gain=+6dB
f=1kHz,V
IN
=1Vrms
BW=400Hz-30kHz
f=10kHz,V
IN
=1Vrms
BW=400Hz-30kHz
-
-
-
9.5
0.0005
0.001
-
-
-
Vrms
%
%
Ver. 0.6E
–3–
MUSES72320
s
ELECTRICAL CHARACTERISTICS
PARAMETER
+
-
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
x
Input/Output Characteristics (Output)
(Ta=25°C, V /V =±15V, V
IN
=2Vrms, f=1kHz, Volume=0dB, V
OUT
: 3pin, 14pin, R
L
=100kΩ, unless otherwise specified)
-118
-100
dBV
Volume=0dB,
-
Output Noise1
V
NO1
(1.26µ)
(10µ)
(Vrms)
Rg=0Ω, A-weight,
dBV
-118
Volume=-111.5dB,
-
-
Output Noise2
V
NO2
(Vrms)
(1.26µ)
Rg=0Ω, A-weight,
s
Logic Control Characteristics
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
x
Digital block Power Supply
Characteristics
D_VDD Terminal
Input Voltage
D_REF Terminal
Input Voltage
V
DVDD
V
DREF
V
DD
17pin Terminal Input
21pin Terminal Input
V
DD
= V
DVDD
– V
DREF
-
V-
3.0
-
-
5.0
0.8*V+
-
6.0
V
V
V
Digital block Supply Voltage
Range
+
-
x
Logic Control Terminal Characteristics
(Ta=25°C, V /V =±15V, V
DREF
=0V, unless otherwise specified)
High Level Input Voltage1
Low Level Input Voltage1
+
-
V
IH1
V
IL1
DATA, CLOCK, LATCH
DATA, CLOCK, LATCH
0.7*V
DD
0
-
-
V
DD
0.3*V
DD
V
V
x
Chip Address / Zero cross Terminal Characteristics
(Ta=25°C, V /V =±15V, V
DREF
=0V, unless otherwise specified)
High Level Input Voltage2
Low Level Input Voltage2
V
IH2
V
IL2
ADR0, ADR1, ADR2, Z/C
ADR0, ADR1, ADR2, Z/C
0.7*V
DD
0
-
-
V
+
V
V
0.3*V
DD
–4–
Ver. 0.6E
MUSES72320
TERMINAL DESCRIPTION
PIN NO.
SYMBOL
FUNCTION
EQUIVALENT CIRCUIT
TERMINAL
DC
VOLTAGE
V+
23
26
InR
InL
Rch input
Lch input
100Ω
V-(sub)
L_REF
R_REF
20kΩ
0V
V+
1.5kΩ
2
4
6
11
13
15
L_REF
R_REF
Lch Reference Voltage
Rch Reference Voltage
0V
V-(sub)
V+
3
14
L+
R+
Lch Opamp non-inverting
input connect terminal
Rch Opamp non-inverting
input connect terminal
0V
V-(sub)
V+
5
12
L-
R-
Lch Opamp inverting input
connect terminal
Rch Opamp inverting input
connect terminal
0V
V-(sub)
Ver. 0.6E
–5–
模拟与混合信号
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