®
FT 5000 Smart Transceiver
FT-X3 Communications Transformer
Troubleshoot Your Network with Ease
The FT 5000 Smart Transceiver is our next-generation chip
for smart networks. It is the key product in the LonWorks® 2.0
platform—the next generation of LonWorks products de-
signed to greatly increase the power and capability of LON-
WORKS enabled devices, while lowering development and
node costs.
The FT 5000 Smart Transceiver integrates a
high-performance Neuron® Core with a free topology twisted-pair trans-
ceiver. Combined with the new low-cost FT-X3 Communications Trans-
former and inexpensive serial memory, the FT 5000 Smart Transceiver
provides a lower-cost, higher-performance LONWORKS solution than
previous-generation FT Smart Transceivers.
Features
• 3.3V operation.
• Higher-performance Neuron® Core —internal system clock scales up
to 80MHz.
• Substantial device price reduction.
• Serial memory interface for
inexpensive external EEPROM
and flash non-volatile memories.
• Supports up to 254 Network
Variables (NVs) and 127 aliases.
• Low-cost surface mount FT-X3
Communications Transformer.
• User-programmable interrupts provide faster response time to external events.
• Includes hardware UART with 16-byte receive and transmit FIFOs.
• 7 mm x 7 mm 48-pin QFN package.
• Supports polarity-insensitive free topology star, daisy chain, bus, loop,
or mixed topology wiring.
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®
• Compliant with TP/FT-10 channels
using FT 3120®/FT 3150® Smart
Transceivers and FTT-10/FTT-10A/
LPT-10/LPT-11 Transceivers.
• 12 I/O pins with 35 programmable
standard I/O models.
• Supports up to 42KB of application
code space.
• 64KB RAM (44KB user-accessible)
and 16KB ROM on-chip memories.
• Unique 48-bit Neuron ID in every
device for network installation and
management.
• Very high common-mode noise
immunity.
• -40°C to +85°C operating tempera-
ture range.
Singly-Terminated Bus Topology
Star Topology
Doubly-Terminated Bus Topology
Transceiver. The Neuron firmware is
pre-programmed into the on-chip ROM.
The FT 5000 Smart Transceiver can also
be configured to read newer firmware
from external memories, allowing the
firmware to be upgraded over time.
Enhanced Performance
Faster system clock.
The internal
system clock for the FT 5000 Smart
Transceiver can be user-configured to
run from 5MHz to 80MHz. The required
external crystal provides a 10MHz clock
frequency, and an internal PLL boosts
the frequency to a maximum of 80MHz
as the internal system clock speed. The
previous-generation Neuron 3120/3150
Core divided the external oscillator
frequency by two to create the internal
system clock. An FT 5000 Smart
Transceiver running with an 80MHz
internal system clock is thus 16 times
faster than a 10MHz Neuron 3120/3150
Core running.
The 5MHz internal system clock mode in
the FT 5000 Smart Transceiver provides
backward compatibility to support
timing-critical applications designed
for the 10MHz FT 3150 or FT 3120 Smart
Transceiver.
The Neuron Core inside the FT 5000
Smart Transceiver includes a built-
in hardware multiplier and divider to
increase the performance of arithmetic
operations.
Support for more network variables.
Because it uses Neuron firmware version
19, the FT 5000 Smart Transceiver
supports applications with up to 254
network variables and 127 aliases for
Neuron hosted devices (devices without
a host microprocessor). A Series 3100
Neuron Chip or Smart Transceiver with
Neuron firmware version 15 or earlier
supports up to 62 network variables and
62 aliases for Neuron hosted devices.
Series 3100 chips with Neuron firmware
version 16 or later support up to 254
network variables. You must use the
NodeBuilder FX Development Tool to
take advantage of 254 network variables.
Interrupts.
The FT 5000 Smart
Transceiver lets developers define
application interrupts to handle
asynchronous events triggered by
selected state changes on any of
the 12 I/O pins, by on-chip hardware
timer-counter units, or by an on-chip
high-performance hardware system
timer. An application uses the Neuron C
interrupt()
clause to define the interrupt
condition and the interrupt task that
handles the condition. The Neuron
C program runs the interrupt task
Free Topology
Loop Topology
= FT device
= Terminatior
Figure 2: Free Topology Network
Configurations
The FT-X3 Communications Transformer
is a surface mount communications
transformer that’s compatible with
both the FT 5000 Smart Transceiver
and the previous-generation FT 3120/
FT 3150 Smart Transceivers. The FT-X3
Communications Transformer provides
equivalent noise
immunity to both the FT-X1 and FT-X2
Communication Transformers, the
previous-generation communication
transformers. However, the FT-X3
Communications Transformer is
not pin-compatible with the FT-X2
Communication Transformer (which
is also a surface mount transformer).
The FT 5000 Smart Transceiver can
also be used with the FT-X1 and FT-X2
Communication Transformers.
Description
The FT 5000 Smart Transceiver includes
three independent 8-bit logical processors
to manage the physical MAC layer, the
network, and the user application. These
are called the Media-Access Control (MAC)
processor, the network (NET) processor,
and the application (APP) processor,
respectively (see Figure 1). At higher
system clock rates, there is also a fourth
processor to handle interrupts.
12
/
2-6
/
2
/
I/O
Serial
Memory
Interface
Comm
Port
External
Transformer
NVM
(SPI or I
2
C)
IRQ CPU
Backward Compatibility
The FT 5000 Smart Transceiver is fully
compliant with the TP/FT-10 channel
and can communicate with devices
that use Echelon’s FTT-10/FTT-10A
Transceivers, FT 3120/FT 3150 Smart
Transceivers, or LPT-10/LPT-11 Link Power
Transceivers.
The Neuron Core in the FT 5000 Smart
Transceiver uses the same instruction
set and architecture as the previous-
generation Neuron Core, with two new
additional instructions for hardware
multiplication and division. The Series
5000 Neuron Core is source code
compatible with applications written
for the Series 3100 Neuron Core.
Applications written for the Series
3100 Neuron Core must be recompiled
with the NodeBuilder® FX Development
Tool or the Mini FX Evaluation Kit before
they can be used with the FT 5000
Smart Transceiver.
The FT 5000 Smart Transceiver uses
Neuron firmware version 19. Firmware
versions prior to version 19 are not
compatible with the FT 5000 Smart
APP CPU
RAM
(64K x 8)
NET CPU
ROM
(16K x 8)
MAC CPU
Clock, Reset,
and Service
XOUT
SVC~
RST~
JTAG
Figure 1: FT 5000 Smart Transceiver Chip
The FT 5000 Smart Transceiver supports
polarity-insensitive cabling using a star,
bus, daisy-chain, loop, or combination
topology (see Figure 2). Thus, installers
don’t have to follow a strict set of wiring
rules imposed by other networking
technologies. Instead, they can install
wiring in the fastest and most cost-
effective manner, thereby saving time
and money. Free topology wiring also
simplifies network expansion by eliminating
restrictions on wire routing, splicing, and
device placement.
XIN
5
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®
whenever the interrupt condition is met.
See the
Neuron C Programmer’s Guide
for
more information about writing interrupt
tasks and handling interrupts.
JTAG.
The FT 5000 Smart Transceiver
provides an interface for the Institute of
Electrical and Electronics Engineers (IEEE)
Standard Test Access Port and Boundary-
Scan Architecture (IEEE 1149.1-1990) of the
Joint Test Action Group (JTAG) to allow
a Series 5000 chip to be included in the
boundary-scan chain for device production
tests. A Boundary Scan Description
Language (BSDL) file for the FT 5000
Smart Transceiver can be downloaded from
Echelon’s Web site.
I/O Pins and Counters
The FT 5000 Smart Transceiver
provides 12 bidirectional I/O pins that
are 5V-tolerant and can be configured to
operate in one or more of 35 predefined
standard input/output models. The chip
also has two 16-bit timer/counters that
reduce the need for external logic and
software development.
Memory Architecture
The FT 5000 Smart Transceiver uses
inexpensive external serial EEPROM and
flash memories for non-volatile application
and data storage, and optionally for future
Neuron firmware upgrades. It has 16KB of
ROM and 64KB (44KB user-accessible)
of RAM on the chip. It has no on-chip
non-volatile memory (EEPROM or flash)
for application use. Each chip, however,
contains its unique Neuron identifier
(Neuron ID) in an on-chip, non-volatile,
read-only memory.
The application code and configuration
data are stored in the external non-
volatile memory (NVM) and copied into
the internal RAM during device reset; the
instructions then execute from internal
RAM. Writes to NVM are shadowed in the
internal RAM and pushed out to external
NVM by the Neuron firmware (see Figure
2). The application does not manage NVM
directly.
External memories supported.
The FT
5000 Smart Transceiver supports two serial
interfaces for accessing off-chip, non-
volatile memories: serial Inter-
Integrated Circuit (I2C) and serial peripheral
interface (SPI). EEPROM and flash memory
devices can use either the I2C interface or
the SPI interface. However, at the time of
publication, there are no serial flash parts
that use the I2C protocol and meet the
required specifications for the Series 5000
external memory interface.
External serial EEPROMs and flash devices,
which are inexpensive and come in very
small form factors, are available from
multiple vendors.
The FT 5000 Smart Transceiver requires at
least 2KB of off-chip memory available in an
EEPROM device to store the configuration
data. The application code can be stored
either in the EEPROM (by using a larger-
capacity EEPROM device) or in a flash
memory device used in addition to the 2KB
(minimum) EEPROM. Thus, the external
memory for the FT 5000 Smart Transceiver
has one of the configurations listed in Table
1:
SCL
Series
5000 Chip
3.3 V
SDA_CS1~
MISO
I
2
C
Slave
(EEPROM)
Figure 3: Using the I
2
C Interface for External
NVM EEPROM Memory
Memory devices supported.
The FT 5000
Smart Transceiver supports any EEPROM
device that uses the SPI or I
2
C protocol,
and meets the clock speed and addressing
requirements described above. While all
EEPROM devices have a uniform write
procedure, flash devices from various
manufacturers differ slightly in their write
procedure. Thus, a small library routine is
stored in the external EEPROM device that
helps the system write successfully to the
external flash device. Echelon has qualified
the following SPI flash memory devices for
use with the FT 5000 Smart Transceiver:
Con-
figura-
tion
1
EEPROM
I
2
C
SPI
SPI
Comments
A single I
2
C EEPROM
memory device,
from 2KB to 64KB
in size.
One I
2
C EEPROM (at
least 2KB in size, up
to 64KB in size, but
the system uses only
the first 2KB of the
EEPROM memory).
One SPI flash
memory device.
☑
2
☑
☑
• Atmel
®
AT25F512B 512-Kilobit
2.7-volt Minimum SPI Serial Flash
Memory.
• Numonyx™ M25P05-A 512-Kbit,
serial flash memory, 50MHz SPI bus
interface.
• Silicon Storage Technology
SST25VF512A 512 Kbit SPI Serial
Flash.
Additional devices may be qualified in
the future.
Memory map.
An FT 5000 Smart
Transceiver has a memory map of 64KB.
A Neuron C application program uses
this memory map to organize its memory
and data access. The memory map is a
logical view of device memory, rather
than a physical view, because the chip’s
processors only directly access RAM. The
memory map divides the FT 5000 Smart
Transceiver’s physical 64KB RAM into
the following types of logical memory, as
shown in Figure 6:
3
☑
A single SPI
EEPROM memory
device, from 2KB to
64KB in size.
One SPI EEPROM (at
least 2KB in size, up
to 64KB in size, but
the system uses only
the first 2KB of the
EEPROM memory).
One SPI flash
memory device.
4
☑ ☑
Table 1: Allowed External Memory Device
Configurations
As Table 1 shows, the FT 5000 Smart
Transceiver supports using a single
EEPROM memory device, or a single
EEPROM memory device plus a single flash
memory device.
If the FT 5000 Smart Transceiver detects
an external flash memory device, the flash
memory represents the entire user non-
volatile memory for the device. That is, any
additional EEPROM memory beyond the
mandatory 2KB is not used.
Using the I
2
C interface.
When using the I
2
C
interface for external EEPROM, the FT
5000 Smart Transceiver is always the
master I
2
C device (see Figure 3). The clock
speed supported for the I
2
C serial memory
interface is 400kHz (fast I
2
C mode). The I
2
C
memory device must specify I
2
C address 0.
Both 1-byte and 2-byte address modes are
supported, but 3-byte addressing mode is
not.
• Neuron firmware image (stored in
on-chip ROM or external NVM).
• On-chip RAM or NVM. Memory
ranges for each are configurable
within the device hardware template.
The non-volatile memory represents
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®
the area shadowed from external
NVM into the RAM.
• On-chip RAM for stack segments
and RAMNEAR data.
• Mandatory external EEPROM that
holds configuration data and non-
volatile application variables.
• Reserved space for system use.
If a 64KB external serial EEPROM or flash
device is used, the maximum allowed size
of application code is 42KB as defined by
extended NVM area in the memory map.
An additional 16KB of the remaining space
can hold an external system firmware
image, in case a future firmware upgrade is
required.
0xF000 to 0xF7FF
0xE800 to 0xEFFF
0xF800 to 0xFFFF
Mandatory EEPROM
On-Chip RAM
Reserved
2 KB
2 KB
2 KB
communications transformer (the FT-X3).
The transformer enables operation in the
presence of high frequency common-mode
noise on unshielded twisted-pair networks.
Properly designed devices can meet
the rigorous Level 3 requirements of EN
61000-4-6 without the need for a network
isolation choke. The transformer also offers
outstanding immunity from magnetic
noise, eliminating the need for protective
magnetic shields in most applications.
The FT 5000 Smart Transceiver and
the FT-X3 Communications Transformer
are designed to be used as a pair, and
therefore must be implemented together in
all designs. No transformer other than
the FT-X3 (or FT-X1 or FT-X2)
communications transformer may be used
with the FT 5000 Smart Transceiver or the
smart transceiver warranty will be void.
Migration Considerations
Most device designs that use the
previous-generation FT 3120/3150 Smart
Transceiver can transition to the FT 5000
Smart Transceiver. However, because
the two generations have different
supply voltage and memory architecture,
hardware redesign of the boards is
required to transition to the
FT 5000 Smart Transceiver.
See the
Series 5000 Chip Data Book
for more information about migrating
device designs for FT 3120/3150
Smart Transceivers to the FT 5000
Smart Transceiver.
SDA_CS1~
VDD1V8
VDD3V3
VDD3V3
RXON
TXON
MOSI
MISO
CS0~
SCK
SCL
CP4
GND PAD
48
47
46
45
44
43
42
41
40
39
38
SVC~
IO0
IO1
IO2
IO3
VDD1V8
IO4
VDD3V3
IO5
IO6
IO7
IO8
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
GND
NC
NETP
AGND
NETN
AVDD3V3
VDD3V3
VIN3V3
RST~
VOUT1V8
GNDPLL
VDDPLL
FT 5000
Smart Transceiver
TRST~
VDD1V8
Dashed line represents Pad (pin 49)
Pad must be connected to GND
Figure 8: FT 5000 Smart Transceiver Pinout
to-end solutions include a comprehensive
set of development tools, network
interfaces, routers, and network tools. In
addition, pre-production design review
services, training, and worldwide technical
support (including onsite support) are
available through Echelon’s Support
technical assistance program.
Extended Memory
(Configurable as:
Extended RAM
or
Non-volatile memory)
42 KB
FT 5000 Smart Transceiver
IC Pin Configuration
FT 5000 Smart Transceiver
IC Pin Descriptions
All digital inputs are low-voltage transistor-
transistor logic (LVTTL) compatible, low
leakage, 5V-tolerant. All digital outputs are
slew-rate limited to reduce Electromagnetic
Interference (EMI).
0x4000 to 0xE7FF
On-Chip ROM
16 KB
End-to-End Solutions
A typical FT 5000 Smart Transceiver-
based device requires a power source,
crystal, external memory, and an I/O
interface to the device being controlled
(see Figure 7 for a typical FT 5000 Smart
Transceiver-based device).
Serial EEPROM
(2KB or larger)
Serial SPI
Flash (optional)
0x0000 to 0x3FFF
Figure 6: FT 5000 Smart Transceiver Memory
Map
Programming memory devices.
Because
the FT 5000 Smart Transceiver does not
have any on-chip user-accessible NVM,
only the external serial EEPROM or flash
devices need to be programmed with the
application and configuration data. The
memory devices can be programmed in
any of the following ways:
Pin
Name
SVC~
IO0
IO1
IO2
IO3
VDD1V8
IO4
VDD3V3
IO5
IO6
IO7
IO8
IO9
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
VDD3V3
Type
Description
Digital I/O Servicelow)
(active
Digital I/O IO0 for I/O Objects
Digital I/O IO1 for I/O Objects
Digital I/O IO2 for I/O Objects
Digital I/O IO3 for I/O Objects
Power
1.8 V Power Input
(from internal
voltage regulator)
3.3 V Power
Sense or Control
Devices: Motors,
Valves, Lights, Relays,
Switches, Controllers
I/O
FT 5000
Smart Transceiver
FT-X3
Communication
Transformer
Crystal
(10 MHz)
Power Source
• In-circuit programming on the
board.
• Over the network.
• Pre-programming before soldering
on the board.
L
ON
W
ORKS
TP/FT-10 Channel
Digital I/O IO4 for I/O Objects
Power
Digital I/O IO5 for I/O Objects
Digital I/O IO6 for I/O Objects
Digital I/O IO7 for I/O Objects
Digital
I/O
Digital
I/O
IO8 for I/O
Objects
IO9 for I/O
Objects
Figure 7: Typical LonWorks based Device
Echelon provides all of the building blocks
required to successfully design and field cost-
effective, robust products based on the FT
5000 Smart Transceivers. Our end-
Noise Immunity
A LonWorks device based on the FT
5000 Smart Transceiver is composed
of two components: the FT 5000
Smart Transceiver and an external
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XOUT
TCK
TMS
TDI
IO10
TDO
IO11
XIN
IO9
®
Pin
Name
IO10
IO11
VDD1V8
TRST~
VDD3V3
TCK
TMS
TDI
TDO
XIN
XOUT
VDDPLL
GNDPLL
VOUT1V8
RST~
VIN3V3
VDD3V3
AVDD3V3
NETN
AGND
NETP
NC
GND
TXON
RXON
CP4
Pin
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Type
Digital
I/O
Description
Pin
Name
CS0~
VDD3V3
VDD3V3
Pin
Type
Description
Param-
eter
1
Description
Current
consumption
in receive
mode
3
5MHz
10MHz
20MHz
40MHz
80MHz
Current
consumption
in transmit
mode
3,4
Minimum Typical Maximum
IO10 for I/O
Objects
Digital I/O IO11 for I/O
Objects
1.8 V Power Input
Power
(from internal
voltage regulator)
Digital
Input
Power
Digital
Input
Digital
Input
Digital
Input
Digital
Output
Oscillator
In
Oscillator
Out
Power
Power
Power
JTAG Test Reset
(active low)
3.3 V Power
JTAG Test Clock
JTAG Test
Mode Select
JTAG Test
Data In
JTAG Test
Data Out
Crystal oscillator
Input
Crystal oscillator
Output
1.8 V Power Input
(from internal
voltage regulator)
Ground
1.8 V Power
Output (of internal
voltage regulator)
40
41
42
SPI slave
select 0 (CS0~,
Digital I/O active low) (for
external memory
connection only)
Power
Power
3.3 V Power
3.3 V Power
I
2
C: serial data (SDA)
SPI: slave
select 1 (CS1~,
active low) (for
external memory
connection only)
1.8 V Power Input
(from internal
voltage regulator)
I
2
C: serial
clock (SCL) (for
external memory
connection only)
SPI master input,
slave output
(MISO) (for
external memory
connection only)
SPI serial clock
(SCK) (for
external memory
connection only)
SPI master
output, slave
input (MOSI) (for
external memory
connection only)
Ground
I
DD3-RX
9 mA
9 mA
15 mA
23 mA
38 mA
I
DD3-RX
+
15 mA
15 mA
15 mA
23 mA
33 mA
52 mA
I
DD3-RX
+ 18mA
SDA_CS1~
43
Digital I/O
I
DD3-TX
VDD1V8
44
Power
Table 3: FT 5000 Smart Transceiver Operating
Conditions
Notes
1. All parameters assume nominal supply
voltage (V
DD3
= 3.3 V ± 0.3 V) and
operating temperature (T
A
between -40ºC
and +85ºC), unless otherwise noted.
2. See
Clock Requirements
in the
Series
5000 Chip Data Book
for more detailed
information about the XIN clock frequency.
3. Assumes no load on digital I/O pins, and
that the I/O lines are not switching.
4. Current consumption in Transmit mode
represents a peak value rather than a
continuous usage value because a Series
5000 device does not typically transmit
data continuously.
SCL
45
Digital I/O
MISO
46
Digital I/O
SCK
47
Digital I/O
Digital I/O Reset (active low)
Power
Power
Power
3.3 V input to
internal voltage
regulator
3.3 V Power
3.3 V Power
MOSI
48
Digital I/O
Ground
Pad
PAD
49
Digital Pin Characteristics
The digital I/O pins (IO0–IO11) have
LVTTL-level inputs. Pins IO0–IO7 also
have low-level-detect latches. The RST~ and
SVC~ pins have internal pull-ups,
and the RST~ pin has hysteresis.
Table 4 below lists the characteristics
of the digital I/O pins, which include IO0–
IO11 and the other digital pins
listed in Table 2.
Communi- Network Port
cations (polarity
insensitive)
Ground
Ground
Communi- Network Port
cations (polarity
insensitive)
N/A
Ground
Digital I/O
Digital I/O
N/A
Do Not Connect
Ground
TxActive for
optional network
activity LED
RxActive for
optional network
activity LED
Connect to V
DD33
through a 4.99
kΩ pullup resistor
Table 2: FT 5000 Smart Transceiver Pin
Description
Electrical Characteristics
FT 5000 Smart Transceiver
Operating Conditions
Param-
eter
1
V
DD3
V
LVI
T
A
f
XIN
Description
Supply
voltage
Low-voltage
indicator trip
point
Ambient
temperature
XIN clock
frequency
2
Minimum Typical Maximum
3.00 V
2.70 V
-40° C
-
10,0000
MHz
3.3 V
3.60 V
2.96 V
+85° C
-
Param-
eter
1
V
OH
V
OL
V
IH
V
IL
Description
Output drive
high at I
OH
=
8 mA
Output drive
low at I
OL
= 8
mA
Input high
level
Input low
level
Mini-
mum
2.4 V
Typical
Maxi-
mum
V
DD3
0.4 V
5.5 V
0.8 V
GND
2.0 V
GND
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