Si3000
V
OICE
B
AND
C
ODEC
Features
Complete voice codec solution includes the following:
WITH
M
ICROPHONE
/S
P E A K E R
D
RIVE
84 dB ADC Dynamic Range
84 dB DAC Dynamic Range
4–12 kHz Sample Rates
30 dB Microphone Pre-Amp
Programmable Input Gain/
Attenuation: –34.5 dB to 12 dB
Programmable Output Gain/
Attenuation: –34.5 dB to 12 dB
Support for 32
Headphones
3:1 Analog Input Mixer
3.3–5.0 V Power Supply
Direct Serial Interface to DSPs
Direct Connection to Si303x/44/56,
serial interface DAA chipsets
Low profile 16-Pin SOIC Package
RoHS-compliant package
available
Ordering Information:
See page 29.
Applications
Modem Voice Channel (DSVD)
Speech Processing
Telephony
General Purpose Analog I/O
Companion chip for FDX
ISOmodems with voice features
Pin Assignments
Si3000
SPKRR
MBIAS
HDST
SDI
SDO
FSYNC
MCLK
SCLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SPKRL
LINEO
GND
V
A
V
D
LINEI
MIC
RESET
Description
The Si3000 is a complete voice band audio codec solution that offers high
integration by incorporating programmable input and output gain/
attenuation, a microphone bias circuit, handset hybrid circuit, and an
output drive for 32
headphones. The Si3000 can be connected directly
to the Si3034, Si3035, Si3044, and Si3056 North American and
international DAA chipsets through their daisy-chaining serial interface. It
also serves as a companion chip to a FAT ISOmodem chipset with voice
features, providing hardware support for a handset and speaker phone.
The device operates from a single 3.3 to 5 V power supply and is
available in a 16-pin small outline package (SOIC).
Functional Block Diagram
Si3000
0/+10/+20/+30 dB
MBIAS
MIC
MCLK
SCLK
FSYNC
SDI
SDO
Digital
Interface
Prog Gain/
Attenuator
High Pass Filter
ADC
0/+10/+20 dB
Handset
Hybrid
0/–6/–12/–18 dB
LINEI
HDST
SPKRR
SPKRL
LINEO
Prog Gain/
Attenuator
DAC
Headphone
Driver
RESET
0/–6/–12/–18 dB
Rev. 1.4 12/10
Copyright © 2010 by Silicon Laboratories
Si3000
Si3000
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1. Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.2. Pre-amp/Microphone Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3. Programmable Input Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4. Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5. Programmable Output Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6. Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7. Speaker Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9. Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10. Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.11. Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.12. Reducing Power-on Pop Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Pin Descriptions: Si3000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7. 16-Pin SOIC Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8. Package Markings (Top Markings) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.1. Si3000-C-GS Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.2. Si3000-C-FS Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.4
3
Si3000
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si3000 Supply Voltage, Analog
2
Si3000 Supply Voltage, Digital
2,3
Symbol
T
A
V
A
V
D
Test Condition
F and K-grade
Min
1
0
3.0
3.0
Typ
25
3.3/5.0
3.3/5.0
Max
1
70
5.25
5.25
Unit
°C
V
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.
2.
The digital supply, V
D,
and analog supply, V
A,
can operate from either 3.3 V or 5.0 V. The Si3000 supports interface to
3.3 V logic when operating from 3.3 V. V
D
must be within 0.6 V of V
A
.
3.
The Si3000 specifications are guaranteed using the typical application circuit (including component tolerance) of
Figure 13.
Table 2. DC Characteristics, V
A
/V
D
= 5 V
(V
A
= 5 V ±5%, V
D
= 5 V ±5%, T
A
= 0 to 70°C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Power Supply Current, Analog
1
Power Supply Current, Digital
2
Total Supply Current, Sleep
Mode
3
Symbol
V
IH
V
IL
V
OH
V
OL
I
L
I
A
I
D
V
A
pin
V
D
pin
I
O
= –2 mA
I
O
= 2 mA
Test Condition
Min
3.5
—
3.5
—
–10
—
—
—
Typ
—
—
—
—
—
6.5
10
—
Max
—
0.8
—
0.4
10
10
15
1.5
Unit
V
V
V
V
µA
mA
mA
mA
Notes:
1.
No loads at DAC outputs, no load at MBIAS, Fs=12.5 kHz.
2.
Slave mode operation, Fs = 12.5 kHz.
3.
All inputs, except MCLK, are held static, and all outputs are unloaded.
Table 3. DC Characteristics, V
A
/V
D
= 3.3 V
(V
A
= 3.3 V ±10%, V
D
= 3.3 V ±10%, T
A
= 0 to 70°C)
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Power Supply Current, Analog
Power Supply Current, Digital
2
Total Supply Current, Sleep Mode
3
Symbol
V
IH
V
IL
V
OH
V
OL
I
L
I
A
I
D
V
A
pin
V
D
pin
I
O
= –2 mA
I
O
= 2 mA
Test Condition
Min
2.4
—
2.4
—
–10
—
—
—
Typ
—
—
—
—
—
6
6
—
Max
—
0.8
—
0.35
10
10
10
1.5
Unit
V
V
V
V
µA
mA
mA
mA
Notes:
1.
No loads at DAC outputs, no load at MBIAS, Fs=12.5 kHz.
2.
Slave mode operation, Fs = 12.5 kHz.
3.
All inputs, except MCLK, are held static, and all outputs are unloaded.
4
Rev. 1.4
Si3000
Table 4. AC Characteristics
Parameter
ADC Resolution
ADC Dynamic Range
1,2
ADC Total Harmonic Distortion
3
V
A
, V
D
= 3.3 V ±10%
ADC Total Harmonic Distortion
3
V
A
, V
D
= 5 V ±5%
ADC Full Scale Level (0 dB gain)
4
ADC Programmable Input Gain
ADC Input Gain Step Size
ADC Freq Response
5
ADC Freq Response
5
ADC Freq Response
Line In Preamp Gain
Mic In Preamp Gain
ADC Input Resistance
ADC Input Capacitance
ADC Gain Drift
DAC Resolution
DAC Dynamic Range
1,2
DAC Total Harmonic Distortion
3
V
A
, V
D
= 3.3 V ±10%
DAC Total Harmonic Distortion
3
V
A
, V
D
= 5 V ±5%
DAC Full Scale Level (0 dB gain)
DAC Programmable Output Gain
V
RX
DACTHD
DACDR
DACTHD
VIN = 1 kHz, –6 dB
VIN=1 kHz,–6 dB,LINEO,600
VIN=1 kHz,–6 dB, SPKR, 60
VIN=1 kHz,–6 dB, HDST, 600
VIN=1 kHz,–3 dB,LINEO,600
VIN=1 kHz,–3 dB, SPKR, 60
VIN=1 kHz,–3 dB, HDST, 600
A
T
VIN = 1 kHz
0 dB Preamp Gain
F
RR
F
RR
F
RR
Low –3 dB corner
300 Hz
3400 Hz
V
RX
ADCTHD
ADCDR
ADCTHD
VIN = 1 kHz, –3 dB
VIN = 1 kHz, –3 dB, MIC/LINEI
VIN = 1 kHz, –3 dB, HDST
VIN = 1 kHz, –3 dB, MIC/LINEI
VIN = 1 kHz, –3 dB, HDST
Vin = 1 kHz
(V
A
, V
D
= 5 V ±5% or 3.3 V ±10%, T
A
= 0 to 70°C)
Symbol
Test Condition
Min
—
80
—
—
—
—
—
–34.5
—
—
–0.1
–0.2
—
—
—
—
—
—
80
—
—
—
—
—
—
—
–34.5
Typ
16
84
–80
–80
–80
–80
1
—
1.5
33
—
—
0/10/20
0/10/20/
30
20
15
0.002
16
84
–76
–72
–80
–76
–72
–80
1
—
Max
—
—
–62
–62
–76
–71
—
12
—
—
0
0
—
—
—
—
—
—
—
–60
–60
–70
–65
–65
–76
—
12
V
rms
dB
dB
V
rms
dB
dB
Hz
dB
dB
dB
dB
k
pF
dB/°C
Bits
dB
dB
dB
Unit
Bits
dB
dB
Notes:
1.
DR = VIN + 20 log (RMS signal/RMS noise). Measurement bandwidth is 300 to 3400 Hz. Valid sample rate ranges
between 4000 and 12000 Hz.
2.
0 dB setting for analog and digital attenuation/gain.
3.
THD = 20 log (RMS distortion/RMS signal). Valid sample rate ranges between 4000 and 12000 Hz.
4.
At 0 dB gain setting, 1 V
rms
input corresponds to –1.5 dB of full scale digital output code.
5.
These characteristics are determined by external components. See Figure 13.
6.
With a 600
load. Output starts clipping with half of full scale digital input, which corresponds to a 0.5 V
rms
output.
Rev. 1.4
5
FPGA/CPLD
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